Dynamic read/write memory circuits with equal-sized dummy and st

Details Dynamic read/write memory circuits with equal-sized dummy and st Dynamic read/write memory circuits with equal-sized dummy and st

1984-07-09

1986-12-30

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Precharge

365210, 365189, G11C 1140

Patent

active

046334432

ABSTRACT:
A semiconductor dynamic read/write memory circuit using one-transistor storage cells and balanced bit lines with differential sense amplifiers employs dummy capacitors which are the same size as the storage capacitors. The dummy cell produces a signal on the bit line half that of the storage cell due to a second dummy capacitor for each dummy cell. One dummy capacitor is precharged to a reference voltage, and the other is predischarged to ground. The net signal is thus equal to that of a capacitor one-half the size of the storage capacitors.

REFERENCES:
patent: 4604534 (1986-08-01), Pricer

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