Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
1999-11-02
2001-04-24
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S049130, C365S230050
Reexamination Certificate
active
06222786
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to electronic memories and in particular to a dynamic random access memory with write-without-restore and systems and methods using the same.
BACKGROUND OF THE INVENTION
Currently available dynamic random access memories (DRAMs) are generally based upon architectures which share the following characteristics. First, the typical general purpose DRAM has a single data port for writing and reading data to and from addressed storage locations (“dual ported” DRAMs are available which provide two data ports, typically one random and one serial port, however, these devices are normally limited to special memory applications). Second, data writes and reads are only made on a location by location basis, with each location typically being one bit, one byte or one word wide. Specifically, in a “random access mode”, an access (read or write) is made to a single location per row address strobe (/RAS) active cycle and in a “page mode” an access is made to a single location per column address strobe (/CAS) or master clock cycle of the row addressed during the given /RAS cycle. Third, no method has generally been established to handle contention problems which arise when simultaneous requests for access are made to the same DRAM unit. Current techniques for handling contention problems depend on the DRAM and/or system architecture selected by the designer and range, for example, from “uniform memory-noncontention” methods to “non-uniform memory access” (NUMA) methods.
Similarly, the system architectures of personal computers (PCs) generally share a number of common features. For example, the vast majority of today's PCs are built around a single central processing unit (CPU), which is the system “master.” All other subsystems, such as the display controller, disk drive controller, and audio controller then operate as slaves to the CPU. This master/slave organization is normally used no matter whether the CPU is a complex instruction set computer (CISC), reduced instruction set computer (RISC), Silicon Graphics MIPS device or Digital Equipment ALPHA device.
Present memory and PC architectures, such as those discussed above, are rapidly becoming inadequate for constructing the fast machines with substantial storage capacity required to run increasingly sophisticated application software. The problem has already been addressed, at least in part, in the mainframe and server environments by the use of multiprocessor (multiprocessing) architectures. Multiprocessing architectures however are not yet cost effective for application in the PC environment. Furthermore, memory contention and bus contention are still significant concerns in any multiprocessing system, let alone in a multiprocessing PC environment.
Thus, the need has arisen for new memory and system architectures to meet the ever increasing demands for faster processing and greater memory capacity. Such architectures should be comprehensive and cost effective. In other words, a total system solution is required.
SUMMARY OF THE INVENTION
A dynamic random access memory includes an array of physical rows and columns of memory cells, the cells of each row coupled to first and second wordlines and the cells of each column coupled to first and second bitlines. A direct input/output data path having a width equal to a width of the rows is provided for simultaneously writing to each of the cells along a selected row using the first wordlines and first bitlines during a single access cycle without restore.
The principles of the present invention have substantial advantages over the prior art. Among other things, since data are written to an entire row or row segment of memory cells at once, the sense and restore operations to the non-accessed cells along the active row, normally part of a conventional write, can be eliminated. This allows write operations to be performed at a substantially greater rate than prior art memories. Moreover, the use of 2T-1C cells supports transparent refresh and precharge. Finally, embodiments include spatial and temporal cache for further increasing the efficiency of data accesses to the memory.
REFERENCES:
patent: 4800530 (1989-01-01), Itoh et al.
patent: 5007022 (1991-04-01), Leigh
patent: 5010519 (1991-04-01), Yoshimoto et al.
patent: 5323350 (1994-06-01), McLaury
patent: 5442588 (1995-08-01), Runas
patent: 5781482 (1998-07-01), Sakata
patent: 5812469 (1998-09-01), Nadeau-Dostie et al.
patent: 5923593 (1999-07-01), Hsu et al.
“Transparent-Refresh DRAM (TReD) Using Dual-Port DRAM Cell” by Sakurai, Nogami, et al. 1988 IEEE Custom Integrated Circ. Conf. p. 4.3.1-4.3.4.
White, et al. “Session 17: Random Acess Memories” IEEE Int'l Solid-State Circ. Conf. Feb. 1980, pp. 230-231.
Kiyoo Itoh, et al. “Limitations & Challenges of Multigigabit DRAM Chip Design” IEEE-Soli-State Cir. vol. 32#5, May 1997, pp. 624-634.
Yashiro Takai, et al. “250 Mbytes/S Synchronous DRAM Using a 3-Stage-Pipelined Architecture” IEEE Solid-State Circ. vol.29#4 Apr. '99 pp 426-430.
NEC Prelim. Data Sheet, MOS Integrated Circuits, 64-M-bit Synchronous DRAM 4-bank, LVTTL for Rev. E. Doc. No. M12 62 1E J VOD SOO (1stEd. pp. 1-82.
R. T. “Tets” Maniwa, “Focus Report: CMOS ASIC's” Integrated Design System Jul. 1997 pp 13.
John H. Mayer “Gearing Up for Systems-On-Silicon Market” Elect. Buyers' News, Aug. 4, 1997, 1069, pp. 52-54.
John L. Hennessy, et al. “Computer Architecture A Quantitative Approach” Chpt. 2 2ndedition, p. 67-82.
B. El-Kareh, et al. “The Evolution of DRAM Cell Technologies” Solid-State Technology May, 1997 p. 89-101.
Holland Wayland Bart
Johnson Gary
Stevens Jason
Waller Craig
Dinh Son T.
Murphy, Esq. James J.
Silicon Aquarius, Inc.
Winstead Sechrest & Minick
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