Dynamic random access memory with well-balanced read-out voltage

Details Dynamic random access memory with well-balanced read-out voltage Dynamic random access memory with well-balanced read-out voltage

1988-05-11

1991-01-01

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Precharge

365210, G11C 700

Patent

active

049823671

ABSTRACT:
A DRAM comprises equalizing capacitance for equalizing the difference between a potential on a bit line to which a selected memory cell is connected and a potential on a reference bit line paired with the bit line when the selected memory cell stores "H" information and that when the selected memory cell stores "L" information, before sensing operation is started. The amplitude of a potential on a selected word line is at an operating power-supply voltage Vcc level of the DRAM.

REFERENCES:
patent: 4780850 (1988-10-01), Miyamoto et al.
patent: 4792922 (1980-12-01), Mimoto et al.
patent: 4799196 (1989-01-01), Takemae
Sunichi Suzuki, "A 128K Word by .times.8 Bit DRAM", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5 (Oct., 1984): 624, 626.
Shozo Saito et al., "A 1 Mb CMOS DRAM with Fast Page and Static Column Modes", 1985 IEEE International Solid-State Circuits Conference (Feb. 15, 1985): 252, 253.
Nicky Chau-Chun Lu, "Half-V.sub.DD Bit-Line Sensing Scheme in CMOS DRAM's", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 4 (Aug. 1984) 451, 454.

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