Dynamic random access memory with bit line equalizing means

Details Dynamic random access memory with bit line equalizing means Dynamic random access memory with bit line equalizing means

1994-06-08

1995-08-22

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Precharge

365205, 365207, 365202, G11C 700

Patent

active

054446627

ABSTRACT:
A dynamic random access memory of the complementary MOS transistor type has memory cells connected between complementary bit lines on one side of a pair of transfer gates and a sense amplifier connected to nodes on the other side of the transfer gates, so that the sense amplifier can be connected to the bit lines and memory cells through the pair of transfer gates. A sense amplifier equalizing circuit and a bit line equalizing circuit are provided on opposite sides of the transfer gates so that the potentials on the bit lines can be equalized independently of equalization of the potentials on the nodes. Accordingly, there is no delay in the equalization due to the transfer gates connecting the nodes to the bit lines. According to another aspect of the invention, the transfer gates each include a pair of MOSFET transistors connected to each other in parallel, wherein one transistor of each pair of MOSFET transistors is an n-channel MOSFET transistor and the other transistor of each pair of MOSFET transistors is a p-channel MOSFET transistor. By, for example, connecting the gate of the NMOS transistor of each transfer to the power source and connecting the gate of each PMOS transistor to the ground, it is possible to prevent erroneous operation of the DRAM from a drop in the gate potential.

REFERENCES:
patent: 5058072 (1991-10-01), Kashimura
patent: 5068831 (1991-11-01), Hoshi et al.
patent: 5202854 (1993-04-01), Koike
patent: 5235547 (1993-08-01), Kobayashi

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