Dynamic random access memory using imperfect isolating...

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C365S149000, C365S208000

Reissue Patent

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RE040552

ABSTRACT:
Apparatus and methods for controlling the sensing of bit lines which facilitates the distribution of bit line charging current to be distributed any time, and facilitates the fast raising of the sense modes to full logic levels. An embodiment is comprised of a plurality of bit storage capacitors, a folded bit line for receiving charge stored on one of the capacitors, having bit line capacitance, a sense amplifier having a pair of sense nodes for sensing a voltage differential across the sense nodes, apparatus connected to the bit line and the sense nodes for imperfectly isolating the sense nodes from the bit line whereby current can leak therethrough, apparatus for enabling the sense amplifier and for disabling the isolating apparatus and thereby removing the isolation between the sense amplifier and the bit line, whereby current passing through the sense amplifier to the sense nodes is enabled to charge the bit line capacitance through the isolating apparatus to predetermined logic voltage level.

REFERENCES:
patent: 2255232 (1941-09-01), Stern
patent: 4117353 (1978-09-01), Butler et al.
patent: 4463440 (1984-07-01), Nishiura et al.
patent: 4608670 (1986-08-01), Duvvury et al.
patent: 4638182 (1987-01-01), McAdams
patent: 4656613 (1987-04-01), Norwood et al.
patent: 4663584 (1987-05-01), Okada et al.
patent: 4769784 (1988-09-01), Doluca et al.
patent: 4780850 (1988-10-01), Miyamoto et al.
patent: 4791616 (1988-12-01), Taguchi et al.
patent: 4795985 (1989-01-01), Gailbreath, Jr.
patent: 4803663 (1989-02-01), Miyamoto et al.
patent: 4812735 (1989-03-01), Sawada et al.
patent: 4833654 (1989-05-01), Suwa et al.
patent: 4839865 (1989-06-01), Sato et al.
patent: 4841180 (1989-06-01), Kraus
patent: 4906914 (1990-03-01), Ohsawa
patent: 4931992 (1990-06-01), Ogihara et al.
patent: 4941128 (1990-07-01), Wada et al.
patent: 4943960 (1990-07-01), Komatsu et al.
patent: 4951256 (1990-08-01), Tobita
patent: 4991142 (1991-02-01), Wang
patent: 4994688 (1991-02-01), Horiguchi et al.
patent: 5010518 (1991-04-01), Toda
patent: 5010523 (1991-04-01), Yamauchi
patent: 5016224 (1991-05-01), Tanaka et al.
patent: 5020031 (1991-05-01), Miyatake
patent: 5022000 (1991-06-01), Terasawa et al.
patent: 5023465 (1991-06-01), Douglas et al.
patent: 5023841 (1991-06-01), Akrout et al.
patent: 5029128 (1991-07-01), Toda
patent: 5029136 (1991-07-01), Tran et al.
patent: 5091885 (1992-02-01), Ohsawa
patent: 5101107 (1992-03-01), Stoot
patent: 5101117 (1992-03-01), Johnson et al.
patent: 5109394 (1992-04-01), Hjerpe et al.
patent: 5111063 (1992-05-01), Iwata
patent: 5127739 (1992-07-01), Duvvury et al.
patent: 5148399 (1992-09-01), Cho et al.
patent: 5177708 (1993-01-01), Furutani et al.
patent: 5189639 (1993-02-01), Miyatake
patent: 5220206 (1993-06-01), Tsang et al.
patent: 5247482 (1993-09-01), Kim
patent: 5252867 (1993-10-01), Sorrells et al.
patent: 5257232 (1993-10-01), Dhong et al.
patent: 5272390 (1993-12-01), Watson, Jr. et al.
patent: 5274586 (1993-12-01), Matsukawa
patent: 5280452 (1994-01-01), Dhong et al.
patent: 5295164 (1994-03-01), Yamamura
patent: 5305259 (1994-04-01), Kim
patent: 5317532 (1994-05-01), Ochii
patent: 5369354 (1994-11-01), Mori
patent: 5371764 (1994-12-01), Gillingham et al.
patent: 5384735 (1995-01-01), Park et al.
patent: 5396465 (1995-03-01), Oh et al.
patent: 5402378 (1995-03-01), Min et al.
patent: 5412615 (1995-05-01), Noro et al.
patent: 5414381 (1995-05-01), Nelson et al.
patent: 5432823 (1995-07-01), Gasbarro et al.
patent: 5436552 (1995-07-01), Kajimoto
patent: 5444203 (1995-08-01), Gunnarsson
patent: 5444662 (1995-08-01), Tanaka et al.
patent: 5459684 (1995-10-01), Nakamura et al.
patent: 5463337 (1995-10-01), Leonowich
patent: 5500824 (1996-03-01), Fink
patent: 5532578 (1996-07-01), Lee
patent: 5534817 (1996-07-01), Suzuki et al.
patent: 5602771 (1997-02-01), Kajigaya et al.
patent: 5610543 (1997-03-01), Chang et al.
patent: 5610550 (1997-03-01), Furutani
patent: 5657481 (1997-08-01), Farmwald et al.
patent: 5673219 (1997-09-01), Hashimoto
patent: 5673232 (1997-09-01), Furutani
patent: 5703475 (1997-12-01), Lee et al.
patent: 5717324 (1998-02-01), Tobita
patent: 5734292 (1998-03-01), Shirai et al.
patent: 5751639 (1998-05-01), Ohsawa
patent: 5757225 (1998-05-01), Tobita
patent: 5771188 (1998-06-01), Fink
patent: 5777501 (1998-07-01), AbouSeido
patent: 5805508 (1998-09-01), Tobita
patent: 5812832 (1998-09-01), Horne et al.
patent: 5815446 (1998-09-01), Tobita
patent: 5841691 (1998-11-01), Fink
patent: 5847597 (1998-12-01), Ooishi et al.
patent: 5856939 (1999-01-01), Seyyedy
patent: 5856951 (1999-01-01), Arimoto et al.
patent: 5880624 (1999-03-01), Koyanagi et al.
patent: 5936898 (1999-08-01), Chi
patent: 5959927 (1999-09-01), Yamagata et al.
patent: 5991226 (1999-11-01), Bhullar
patent: 6021063 (2000-02-01), Tai
patent: 6067592 (2000-05-01), Farmwald et al.
patent: 6087868 (2000-07-01), Millar
patent: 6151242 (2000-11-01), Takashima
patent: 6314052 (2001-11-01), Foss et al.
patent: 6327318 (2001-12-01), Bhullar et al.
patent: 6510503 (2003-01-01), Gillingham et al.
patent: 6657918 (2003-12-01), Foss et al.
patent: 02549801 (1988-05-01), None
patent: 0 254 980 (1991-09-01), None
patent: 62-150590 (1987-07-01), None
1992 Xerox Presentation re. use of on-chip DLL.
Adler, E., “The Evolution of IBM CMOS DRAM Technology,”IBM J. Res. Develop., vol. 39 No. 1/2, Jan./Mar. 1995, p. 169.
Anceau, “A Synchoronous Approach for Clocking VLSI Systems,”IEEE journal of Solid-State Circuits, vol. SC-17, No. 1 (Feb. 1982).
Chen, “Designing On-Chip Clock Generators,” Circuits and Devices, Jul. 1992, pp. 32-36.
Chou, Shizuo, et al., “A 60-ns 16M-bit DRAM With a Minimized Sensing Delay Caused by Bit-Line Stray Capacitance,”IEEE Journal of Soild State Circuits ,vol. 24, No. 5, Oct. 1989, pp. 1176-1178.
Foss, R.C., et al., “Application of a High-Voltage Pumped Supply for Low-Power DRAM,”IEEE 1992 Symposium on VLSI Circuits of Technical Papers, pp. 106-107.
Fujii, Syuso, et al., “A 45-ns 16-Mbit DRAM with Triple-Well Structure,”IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1170-1174.
Gasbarro, et al., “Techniques for Characterizing DRAMS With a 500 MHz Interface,” International Test Conference, Oct. 1994, pp. 516-525.
Gasbarro, “Testing High Speed DRAMS,” International Test Conference, Oct. 1994, p. 361.
Gillingham, Peter, et al., “High-Speed, High-Reliability Circuit Design for Megabit DRAM,”IEEE Journal of Solid-State Circuits, vol. 26, No. 8, Aug, 1991, pp. 1171-1175.
Horowitz, Mark, “Clocking Strategies in High Performance Processors,”1992 Symposium on VLSI Circuits Digest of Technical Papers, pp. 50-53.
Horowitz, M., et al., “PLL Design for a 500 MB/s Interface,” ISSCC Digest of Technical Papers (Feb. 1993).
Johnson, et al., “A Variable Delay Line PLL for CPU-Coprocessor Synchronization,”IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct., 1988, pp. 1218-1223.
Kim, S., et al., “A Pseudo-Synchronous Skew-Insensitive I/O Scheme for High Bandwidth Memories,”1994 Symposium on VLSI Circuits Digest of Technical Papers, pp. 41-42.
Menasce, V., et al., “A Fully Digital Phase Locked Loop,” Canadian Conference on VLSI, Oct. 1990, pp. 9.4.1-9.4.8.
NEC, PLL Enable Mode, JC-42.3 (Sep. 14, 1994) (FIN 023321-023377).
Patent Application for Delay Locked Loop (DLL) Implementation in a Synchronous Dynamic Random Access Memory, Sep. 29, 1994 (MTI0000118755-118768).
Przybylski, Steven,New DRAM Technologies, A Comprehensive Analysis of the New Architectures, MicroDesign Resources, Sebastopol, CA, (1994).
Rambus document RM 2744932-33, details Rambus making certain technical information publicly available on the internet in Nov. 1993.
Rambus Product Catalog, by Rambus, Inc., 1993.
RDRAM Reference Manual, by Rambus, Inc., 1993.
Schanke, Morten, “Proposal for Clock Distribution in SCI,” May 5, 1989.
Sidiropoulos, Stefanos, et al., “A CMOS 500 Mbps/pin synchronous point to

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