Dynamic random access memory structure

Details Dynamic random access memory structure Dynamic random access memory structure

2000-01-06

2001-03-20

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S303000, C257S304000, C257S306000

Reexamination Certificate

active

06204528

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) structure. More particularly, the present invention relates to a vertical DRAM structure.
2. Description of the Related Art
As the level of integration of semiconductor devices increases, dimensions of circuit devices must be reduced according to design rules. Theoretically, line width of gates can be reduced ad infinitum. In practice, however, line width is limited by the resolution in photolithographic operations as well as length of device channel. Since a source/drain region is formed using the gate line as an ion mask in an ion implantation, line width of the gate is almost equivalent to length of the channel. Although the reduction of channel length is able to increase drifting speed of carriers from one source/drain terminal to the next, the hot carrier effect will intensify resulting in a higher rate of device failure. Hence, an upper limit is set on the possible level of integration for conventional DRAM devices.
SUMMARY OF THE INVENTION
This invention also provides a dynamic random access memory structure. The structure includes a substrate having protruding sections and recessed sections, in which the protruding sections have sidewalls and a substrate surface is located between the protruding sections and the recessed sections. A gate oxide layer is formed on the sidewalls of the protruding sections and on the surfaces between the protruding sections and the recessed sections. A doped region is formed near the bottom of each protruding section, and these doped regions serve as buried bit lines. A channel region is formed in the protruding section and a gate electrode is formed on each side of the channel region. A storage electrode is connected to the other end of the protruding section and a word line is connected to the gate electrode. The word line and the buried bit line are perpendicular to each other. The aforementioned structure further includes a shallow trench isolation structure in the recessed section of the substrate.
Accordingly, the present invention is to provide a dynamic random access memory (DRAM) structure capable of increasing the level of integration for DRAM devices. In addition, the invention also provides a DRAM structure capable of packing more devices onto a piece of silicon chip so that the level of device integration is increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5017977 (1991-05-01), Richardson
patent: 5429973 (1995-07-01), Hong
patent: 6025221 (2000-02-01), Brown
patent: 6075265 (2000-06-01), Goebel et al.

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