Dynamic random access memory of semiconductor device and...

Details Dynamic random access memory of semiconductor device and... Dynamic random access memory of semiconductor device and...

2007-06-12

2007-06-12

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C257S296000, C257S369000, C257SE27084

Reexamination Certificate

active

11165180

ABSTRACT:
The present invention discloses an improved DRAM of semiconductor device and method for manufacturing the same wherein an ONO (oxide-nitride-oxide) structure for trapping electrons or holes used in a non-volatile memory is employed in a gate insulating film of the DRAM to reduce impurity concentrations of a channel region and a well region.

REFERENCES:
patent: 6955952 (2005-10-01), Yeo et al.
patent: 7067369 (2006-06-01), Lee
patent: 7087476 (2006-08-01), Metz et al.
patent: 2005/0205939 (2005-09-01), Lee et al.
patent: 2005/0230740 (2005-10-01), Lee
patent: 2006/0008959 (2006-01-01), Hagemeyer et al.
patent: 2006/0157755 (2006-07-01), Lee et al.
Jiankang Bu et al., “Retention Reliability Enhanced SONOS NVSM with Scaled Programming Voltage”, IEEE, 2002, pp. 5-2383-5-2389, vol. 5.
Takeshi Hamamoto et al., On the Retention Time Distribution of Dynamic Random Access Memory (DRAM); IEEE, Jun. 1998, pp. 1300-1309, vol. 45, No. 6.

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