Dynamic random access memory having sequential word line refresh

Details Dynamic random access memory having sequential word line refresh Dynamic random access memory having sequential word line refresh

1996-08-22

1998-02-03

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Data refresh

36523006, 36523008, 365236, G11C 700, G11C 800

Patent

active

057152063

ABSTRACT:
A DRAM includes a refresh controller including a clock control section for producing a refresh mode signal in response to an external control clock signal, a refresh logic section for producing an enable signal in response to the refresh mode signal, a refresh counter for sequentially producing a first plurality of row address signals during an active period of a row address strobe signal in response to the enable signal, a row address buffer for producing a second plurality of row address signals in response to the row address signals, and a row decoder including a plurality of word line drivers which sequentially decode the second plurality of row address signals provided from the row address buffer and sequentially enables word lines corresponding to the decoded row address signals.

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