Dynamic random access memory having selectively activated subarr

Details Dynamic random access memory having selectively activated subarr Dynamic random access memory having selectively activated subarr

1987-09-09

1989-05-23

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Precharge

365189, 3652385, G11C 700

Patent

active

048336530

ABSTRACT:
A DRAM of a partially activating system, in which, in an active cycle, sense amplifiers (91a, 91b) are inactivated and the potential on each pair of bit lines (BLA1, BLA1, BLA2, BLA2) is equalized early in the active cycle only for a subarray to be accessed while the potential is not equalized and the sense amplifiers are kept to be activated for a subarray not to be accessed. At the time of an inactive cycle, all the sense amplifiers (91a, 91b) are activated, and the bit lines (BLA1, BLA1, BLA2, BLA2) in the memory cell array are at an "H" or "L" level depending on information read out in the previous active cycle.

REFERENCES:
patent: 4551820 (1985-11-01), Matsuura
IEEE Journal, "The Design and Performance of CMOS 256K Bit DRAM Devices", by A. M. R. Mohsen et al., pp. 610-618, V. SC-19, No. 5, Oct. 1984.
ISSCC 86, "An Experimental 4Mb CMOS DRAM", by Tohru Furuyama et al., pp. 272-273, Feb. 21, 1986.
Nikkei Microdevices: "DRAM Skills Having 4M Bits", by T. Furuyama et al., 3/1986, pp. 97-108.

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