Dynamic random access memory having reduced array voltage

Details Dynamic random access memory having reduced array voltage Dynamic random access memory having reduced array voltage

1999-02-18

2000-10-31

Hoang, Huan

Static information storage and retrieval

Read/write circuit

Including signal clamping

365205, 365149, G11C 700

Patent

active

061412597

ABSTRACT:
A random access memory (RAM) having a bipolar reduction in array operating voltage is disclosed. In a preferred embodiment, a clamping transfer gate circuit (414) couple pairs of bit lines (BL and /BL) to pairs of sense nodes (410 and 412). The clamping transfer gate circuit (414) includes an n-channel MOS transistor (N401 and N402) in series with a p-channel MOS transistor (P401 and P402) coupling a bit line (BL or /BL) to a sense node (410 or 412). The gates of the n-channel transistors (N401 and N402) are driven by the high power supply voltage (VDD), and the gates of the p-channel transistors (P401 and P402) are driven by the low power supply voltage (VSS). A sense amplifier circuit (418) drives the sense node pair (410 and 412) to opposite power supply voltages (VDD and VSS). The n-channel transistors (N401 and N402) in the clamping transfer gate circuit (414) clamp the voltage on the bit lines (BL and /BL) to a maximum level of VDD-Vtn, where Vtn is the n-channel transistor threshold voltage. The p-channel transistors (P401 and P402) in the clamping transfer gate circuit (414) clamp the voltage on the bit lines (BL and /BL) to a minimum level of VSS+Vtp, where Vtp is the p-channel transistor threshold voltage. For dynamic RAM applications, memory cells having a higher charge storage capability are disclosed to compensate for the lower array voltages used during refresh operations.

REFERENCES:
patent: 5459345 (1995-10-01), Okudaira et al.
patent: 5581436 (1996-12-01), Summerfelt et al.
patent: 5856939 (1999-01-01), Seyyedy
patent: 5972722 (1999-10-01), Visokay et al.

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