Dynamic random access memory (DRAM) cells with repressed ferroel

Details Dynamic random access memory (DRAM) cells with repressed ferroel Dynamic random access memory (DRAM) cells with repressed ferroel

1999-08-30

2000-10-31

Phan, Trong

Static information storage and retrieval

Systems using particular element

Ferroelectric

365149, G11C 1122

Patent

active

061412384

ABSTRACT:
A memory cell having first and second operating modes includes a transistor comprising a gate adjacent to a channel region coupling source and drain regions, a digitline coupled to one of the source and drain regions, a storage capacitor coupled to the other of the source and drain regions, a ferroelectric capacitor, and a wordline coupled to the gate by the ferroelectric capacitor. Preferably, data is written to and read out of the storage capacitor during the first operating mode and written to and read out of the ferroelectric capacitor during the second mode of operation. A memory cell array, a memory module, and a processor based system can all be fabricated from this memory cell. A method for reading data out of the memory cell in first and second operating modes is also described.

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