Dynamic random access memory device provided with test circuit f

Details Dynamic random access memory device provided with test circuit f Dynamic random access memory device provided with test circuit f

1984-06-15

1987-06-09

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Data refresh

365201, 371 21, G11C 700

Patent

active

046725830

ABSTRACT:
A dynamic random access memory device is equipped with a test circuit for testing an internal refresh circuit. In a test mode, the content of an internal address counter is supplied to both the row of column address decoders, by which one memory cell disposed on the diagonal in a memory cell array is designated. Further, data is written into the designated memory cell from outside of the memory device, and the data stored in the designated memory cell is then read out to check whether the read-out signal is coincident with the written data.

REFERENCES:
patent: 4347589 (1982-08-01), Proebsting
patent: 4380805 (1983-04-01), Proebsting

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