Dynamic random access memory device having precharge circuit for

Details Dynamic random access memory device having precharge circuit for Dynamic random access memory device having precharge circuit for

1993-10-18

1994-10-18

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Precharge

36518909, 36518911, 365204, 365208, 36523006, G11C 702

Patent

active

053574745

ABSTRACT:
A semiconductor memory device comprises read-out circuits responsive to first column address decoded signals for transferring data bits from selected bit lines to data line pairs, selector circuits responsive to second column address decoded signals for transferring a data bit from selected one of the data line pairs to a read data amplifier circuit and a precharge circuit coupled between a source of power voltage level and the data line pairs for charging the selected data line pair before transmission of the data bit to the selected data line pair, and the precharge circuit isolates the data line pair from the source of power voltage level so that potential difference indicative of the data bit rapidly takes place on the selected data line pair.

REFERENCES:
patent: 5058072 (1991-10-01), Kashimura
patent: 5274590 (1993-12-01), Kashimura
Y. Nakagome et al., "A 1.5V Circuit Technology for 64Mb DRAMs", 1990 IEEE Symposium on VLSI Circuits, pp. 17-18.

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