Dynamic random access memory device and method of...

Details Dynamic random access memory device and method of... Dynamic random access memory device and method of...

2011-02-22

2011-02-22

Lam, David (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S222000, C365S230080

Reexamination Certificate

active

07894282

ABSTRACT:
Provided are a dynamic random access memory device having reduced power consumption and a method of determining a refresh cycle of the dynamic random access memory device. The method includes: selecting one or more monitoring bits during first through n-th self refresh cycles, where “n” is a natural number equal to or greater than one; detecting whether the monitoring bits have errors during (n+1)-th through m-th self refresh cycles, where “m” is a natural number equal to or greater than n+1; and adjusting an (m+1)-th self refresh cycle according to whether the monitoring bits have errors.

REFERENCES:
patent: 4935900 (1990-06-01), Ohsawa
patent: 6697992 (2004-02-01), Ito et al.
patent: 6795362 (2004-09-01), Nakai et al.
patent: 7319612 (2008-01-01), Babb et al.
patent: 7458004 (2008-11-01), Takahashi
patent: 7477563 (2009-01-01), Kang et al.
patent: 2002025299 (2002-01-01), None
patent: 2002056671 (2002-02-01), None
patent: 2003132677 (2003-05-01), None
patent: 1020050078242 (2005-08-01), None

Affiliated with

Also associated with

Rating

Dynamic random access memory device and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic random access memory device and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic random access memory device and method of... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2637318