Dynamic random access memory cell layout and fabrication...

Details Dynamic random access memory cell layout and fabrication... Dynamic random access memory cell layout and fabrication...

2005-07-19

2005-07-19

Tran, Thien F (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S243000, C438S248000, C438S249000, C438S386000

Reexamination Certificate

active

06919245

ABSTRACT:
A dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof. An active area comprises two vertical transistors, a common bitline contact and two deep trenches. The first vertical transistor is formed on a region where the first deep trench is partially overlapped with the first gate conductive line. The second vertical transistor is formed on a region where the second deep trench is partially overlapped with the second gate conductive line.

REFERENCES:
patent: 6399447 (2002-06-01), Clevenger et al.

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