Dynamic random access memory and method for equalizing sense amp

Details Dynamic random access memory and method for equalizing sense amp Dynamic random access memory and method for equalizing sense amp

1988-10-19

1993-01-05

Gossage, G. A.

Static information storage and retrieval

Read/write circuit

Precharge

365205, G11C 11407

Patent

active

051777088

ABSTRACT:
In a dynamic random access memory (DRAM) having a sense amplifier of complementary metal oxide semiconductor (CMOS) type, switching transistors are provided for setting the bit line potential and the potential of the sense amplifier driving signal line at the same potential, namely, a half of the voltage applied to the bit line in writing "H", during the bit line equalizing period.

REFERENCES:
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patent: 4608670 (1986-08-01), Duvvury et al.
patent: 4780850 (1987-11-01), Miyamoto et al.
"A 256Kb CMOS Pseudo SRAM", Hiroshi Kawamoto et al., 1984 IEEE Int'l Solid State Conf., Digest of Technical Papers, Feb. 24, 1984, pp. 276-277.
"FAM 18.4: A Sub 100ns 256K DRAM in CMOS III Technology", Roger I. Kung et al., IEEE International Solid-State Circuits Conference, Feb. 1984, pp. 278-278 & 354, Digest of Technical Papers.
IECE Japan National Conference Proceedings, p. 2-205, THPM 439.
"A 64Kbit MOS RAM", Hisanori Yoshimura et al., IEEE International Solid-State Circuits Conference, Feb. 1978, pp. 148-149, Digest of Technical Papers.
"A 64K MOS RAM Design", N. Ieda et al., 9th Conference on Solid State Devices, Tokyo, 1977; Japanese Journal of Applied Physics, vol. 17 (1978).
"Simplified Peripheral Circuits for a Marginally Testable 4K RAM", Richard Foss et al., IEEE International Solid-State Circuits Conference, Feb. 1975, pp. 102-103, Digest of Technical Papers.

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