Dynamic RAM organization for reducing peak current

Details Dynamic RAM organization for reducing peak current Dynamic RAM organization for reducing peak current

1979-02-09

1980-09-09

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365194, 365203, G11C 702

Patent

active

042221129

ABSTRACT:
An MOS dynamic random access memory (RAM) includes an array of memory cells arranged in rows and columns. The array is divided into two or more sub-arrays. During an operating cycle latching of the sense amplifiers in the sub-arrays is staggered to avoid coincidence of current peaks each arising when the sense amplifiers in one of the sub-arrays are simultaneously latched. Latching takes place first in a sub-array in which a cell is selected. Recovery of the column conductors in the sub-arrays is also staggered to avoid coincidence of current peaks each occurring when one of the sub-arrays is recovered. The sub-array in which a cell is selected is recovered last.

REFERENCES:
patent: 3866061 (1975-02-01), Wen et al.
patent: 4090096 (1978-05-01), Nagami
patent: 4162540 (1979-07-01), Ando

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