Dynamic RAM memory

Details Dynamic RAM memory Dynamic RAM memory

1984-06-18

1987-06-23

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, G11C 1140

Patent

active

046758488

ABSTRACT:
There is provided an improved MOS dynamic random access memory (DRAM) device having an array of dynamic RAM cells accessed by word and bit lines. Each memory cell comprises a single field-effect transistor coupled by its source to the gate of an MOS storage capacitor. The word lines are coupled to their respective memory cells at the gate of the field-effect transistor therein, while the bit lines are coupled to their respective memory cells at the drain of the field-effect transistor. The bit lines are organized into pairs of adjacent polysilicon lines that are coupled to all the memory cells on both sides of the bit lines in an alternating configuration. The word lines are coupled to alternating pairs of cells on opposite sides of the word lines.

REFERENCES:
patent: 3209337 (1965-09-01), Crawford
patent: 3965459 (1976-06-01), Spencer et al.

Affiliated with

Also associated with

Rating

Dynamic RAM memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic RAM memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic RAM memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-726442