Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1982-12-23
1985-11-05
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365210, G11C 1140
Patent
active
045518203
ABSTRACT:
In a dynamic RAM having a memory array of a folded bit line arrangement, the memory array has a plurality of bit line pairs. A plurality of word lines and dummy word lines cross each of the bit line pairs so as to apply coupling noises of the same phase to the bit lines constituting each of the bit line pairs. The levels of the coupling noises applied to the bit lines constituting each of the bit line pairs, however, are also affected by the stray capacitance between the bit lines. Since the bit line disposed at an end part of the memory array has only one adjacent bit line disposed on one side thereof, only a relatively small stray capacitance is connected to the bit line. This causes the coupling noise between bit lines at the bit line disposed at an end part of the memory array to be different than the degree of coupling noise between other bit lines in the array. To overcome the unbalance this causes, an additional dummy bit line is disposed at an end part of the memory array in order to increase the stray capacitance connected to the bit line disposed at the end part of the memory array. Consequently, common mode noises at levels substantially equal to each other are applied to all the bit line pairs. A differential type sense amplifier connected to each of the bit line pairs does not respond to the common mode noise. Accordingly, the minute data signal set by a selected memory cell and a dummy memory cell in reading out data is amplified with substantially no deleterious effect being caused by noise.
REFERENCES:
patent: 4044340 (1977-08-01), Itoh
patent: 4045783 (1977-08-01), Harland
patent: 4122546 (1978-10-01), von Basse et al.
patent: 4371956 (1983-02-01), Maeda et al.
patent: 4476547 (1984-10-01), Miyasaka
Japanese Laid-Open Patent Application No. 148056/1974, Jun. 28, 1976.
Hitachi , Ltd.
Hitachi Microcomputer & Engineering, Ltd.
Popek Joseph A.
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