Dynamic ram having multiplexed twin I/O line pairs

Details Dynamic ram having multiplexed twin I/O line pairs Dynamic ram having multiplexed twin I/O line pairs

1986-09-16

1988-06-28

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365203, 365230, G11C 700

Patent

active

047544333

ABSTRACT:
A dynamic random access memory (DRAM) is comprised of a first and a second input/output (I/O) bus, a first and a second I/O sense amplifier, and a first and a second I/O bus precharge circuit. A control circuit is responsive to the state of a mode control signal for enabling the operation of the I/O buses and the precharge circuits such that in one mode of operation the DRAM operates in a conventional single bit per CAS cycle page mode. In a second mode of operation a high speed dual bit per CAS cycle page mode is achieved, wherein the I/O buses are alternately enabled, one being enabled when CAS is asserted and the other being enabled when CAS is deasserted. The dual bit mode of operation provides also for precharging the I/O bus which is not enabled during the period when the other bus is enabled. Thus, in the dual bit mode of operation data transfers to or from the DRAM occur both when CAS is asserted and also when CAS is deasserted, thereby doubling the data transfer rate over that of the conventional page mode of operation.

REFERENCES:
patent: 4672587 (1987-06-01), Geiger et al.

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