Dynamic RAM having full-sized dummy cell

Details Dynamic RAM having full-sized dummy cell Dynamic RAM having full-sized dummy cell

1986-11-12

1988-03-29

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Differential sensing

365203, G11C 1140, G11C 1300

Patent

active

047348909

ABSTRACT:
A dynamic RAM has dummy capacitors (C6, C7) having the same capacitance as a memory capacitor connected to a pair of bit lines (BL1, BL1), respectively. During an active period, respective dummy capacitors (C6, C7) are charged to the H level and L level, which are signal levels of the bit lines (BL1, BL1) and during precharge period, both dummy capacitors are equalized. Since both dummy capacitors (C6, C7) respectively connected to a pair of bit lines (BL1, BL1) are equalized during precharge period, so that the stored charge values of the dummy capacitors (C6, C7) both become the intermediate value of the ground level and supply potential level.

REFERENCES:
patent: 4648074 (1987-03-01), Pollachek

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