Patent
1983-01-10
1987-02-03
Edlow, Martin H.
357 38, 357 43, 357 41, H01L 2978
Patent
active
046411631
ABSTRACT:
MIS-FET assembly, including a first MIS-FET having a semiconductor substrate of a first conductivity type with first and second surfaces, at least one channel zone of a second conductivity type opposite the first conductivity type being embedded in the first surface of the substrate, a source zone of the first conductivity type being embedded in the channel zone, a drain zone adjoining the first surface of the substrate, a drain electrode connected to the second surface of the substrate, an insulating layer disposed on the first surface of the substrate, at least one gate electrode disposed on the insulating layer, and at least one injector zone of the second conductivity type being embedded in the first surface of the substrate defining a pn-junction between the injector zone and the drain zone being disposed under the at least one gate electrode, and a second MIS-FET having a gate electrode and having a source and drain electrodes defining a source-drain path being connected between the injector zone of the MIS-FET and the drain zone of the first MIS-FET, the gate electrode of the second MIS-FET being electrically connected to the at least one gate electrode of the first MIS-FET.
REFERENCES:
patent: 4199774 (1980-04-01), Plummer
patent: 4364073 (1982-12-01), Becke et al.
patent: 4454527 (1984-06-01), Patalong
patent: 4471372 (1984-09-01), Tihanyi
patent: 4485390 (1984-11-01), Jones et al.
Edlow Martin H.
Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft
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