Dynamic RAM device having a separate test mode capability

Details Dynamic RAM device having a separate test mode capability Dynamic RAM device having a separate test mode capability

1987-04-22

1989-03-07

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Testing

365200, 365233, 365193, 371 21, G11C 700, G11C 2900, G11C 800

Patent

active

048112992

ABSTRACT:
Disclosed is a dynamic RAM device capable of initiating and cancelling the test mode in response to the combinations of the row address and column address strobe signals with the write enable signal, which combinations are left unused in the normal operating mode, instead of increasing the number of external control signals.

REFERENCES:
patent: 4414665 (1983-11-01), Kimura et al.
patent: 4653030 (1987-03-01), Tachibana et al.
patent: 4656610 (1987-04-01), Yoshida et al.
patent: 4672583 (1987-06-01), Nakaizumi
patent: 4752914 (1988-06-01), Nakano et al.

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