Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2007-09-18
2007-09-18
Mai, Son L. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Precharge
C365S156000, C365S190000
Reexamination Certificate
active
11041345
ABSTRACT:
Dynamic control of a pre-charge level particularly for memory cells is described. In one example, a circuit block has pre-charge node and a power supply is coupled to the pre-charge node to provide either a first power level or a second power level when the circuit block is not active. The first power level may be a pre-charge mode power level and the second power level may be a sleep mode power level.
REFERENCES:
patent: 4899317 (1990-02-01), Hoekstra et al.
patent: 5604705 (1997-02-01), Ackland et al.
patent: 5995431 (1999-11-01), Inui et al.
patent: 6292418 (2001-09-01), Kawashima et al.
patent: 6549450 (2003-04-01), Hsu et al.
patent: 6683805 (2004-01-01), Joshi et al.
patent: 6922370 (2005-07-01), Deng et al.
patent: 7116593 (2006-10-01), Hanzawa et al.
patent: 2004/0243758 (2004-12-01), Notani
patent: 2005/0128852 (2005-06-01), Deng et al.
patent: 2005/0185474 (2005-08-01), Atwood et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Mai Son L.
LandOfFree
Dynamic pre-charge level control in semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dynamic pre-charge level control in semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic pre-charge level control in semiconductor devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3788267