Dynamic multi-Vcc scheme for SRAM cell stability control

Details Dynamic multi-Vcc scheme for SRAM cell stability control Dynamic multi-Vcc scheme for SRAM cell stability control

2006-07-18

2006-07-18

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read/write circuit

Multiplexing

C365S230020, C365S226000

Reexamination Certificate

active

07079426

ABSTRACT:
A dynamic multi-voltage memory array features SRAM cells that are subjected to different biasing conditions, depending on the operating mode of the cells. The selected SRAM cell receives a first voltage when a read operation is performed, and receives a second voltage when a write operation is performed. By biasing the cell differently for the two distinct operations, a total decoupling of the read and write operations is achieved. The disclosed memory array, as well as future SRAM designs incorporating the multi-voltage capability thus avoid the conflicting requirements of read and write operations. Random single-bit failures of the memory array are reduced, due to the improvement in read stability and write margin.

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