Dynamic memory with intermediate column derode

Details Dynamic memory with intermediate column derode Dynamic memory with intermediate column derode

1984-07-02

1986-12-16

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, G11C 700

Patent

active

046302409

ABSTRACT:
A dynamic read/write memory array has a column decode and data input/output arrangement constructed to compensate for large capacitive loads in the I/O circuitry. In a first stage, a buffer is employed between sense amplifiers and segmented intermediate I/O lines. Each segment is a small fraction of the I/O load. First-level column decoding selects one column for each segment. A second level of column decoding employs tri-state buffers which can only be activated during a read with the proper column address. When writing, all buffers are in the high impedance state for reading while the selected buffer is written into through decoded pass gates.

REFERENCES:
patent: 4094012 (1978-06-01), Perlegos et al.
patent: 4533843 (1985-08-01), McAlexander, III

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