Dynamic memory with improved dummy cell circuitry

Details Dynamic memory with improved dummy cell circuitry Dynamic memory with improved dummy cell circuitry

1984-07-11

1987-04-14

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Precharge

365149, 365204, 365210, G11C 1140, G11C 1300

Patent

active

046583823

ABSTRACT:
A semiconductor read/write memory device of the type using dynamic one-transistor storage cells employs dummy capacitors which are the same size as the storage capacitors, and these dummy capacitors are precharged to a reference voltage level less than half the supply voltage. A voltage divider sets the precharge level, but this divider is shunted by a control device initially so the dummy capacitors are quickly discharged to the reference level. A comparator with differential inputs determines when the reference level has reached the proper value, then the control device and the comparator are shut off to reduce power, and the reference level maintained by the voltage divider. The dummy capacitor precharge starts during the later part of an active cycle, so the specified cycle time can be minimized.

REFERENCES:
patent: 3760381 (1973-09-01), Yao
patent: 3909631 (1975-09-01), Kitagawa
patent: 3942160 (1976-03-01), Yu
patent: 4363111 (1982-12-01), Heightley et al.
patent: 4370575 (1983-01-01), McAlexander, III et al.
patent: 4458336 (1984-07-01), Takemae
patent: 4506351 (1985-03-01), Scheuerlein et al.

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