Dynamic memory with high speed nibble mode

Details Dynamic memory with high speed nibble mode Dynamic memory with high speed nibble mode

1983-07-08

1986-01-28

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, G11C 1300

Patent

active

045675791

ABSTRACT:
A semiconductor dynamic memory device has an array of one-transistor cells, with row and column decode to produce a 4-bit wide input or output. Single-bit data-in and data-out terminals for the device may be coupled to the 4-bit array input/output in a sequential mode. The row and column addresses are latched when RAS and CAS drop, and this includes the address of the starting bit within the 4-bit sequence. The other three bits follow as CAS is cycled. This starting address is used to set a bit in a 4-bit ring counter, which is then used to cycle through the sequence.

REFERENCES:
patent: 4239993 (1980-12-01), McAlexander, III
patent: 4344156 (1982-10-01), Eaton, Jr. et al.
patent: 4484308 (1984-11-01), Lewandowski et al.

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