Dynamic memory bit line precharge scheme

Details Dynamic memory bit line precharge scheme Dynamic memory bit line precharge scheme

1991-04-05

1993-08-03

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Precharge

365149, G11C 700

Patent

active

052335607

ABSTRACT:
A method and apparatus for precharging DRAM bit lines and data buses from the same voltage source, eliminating a separate bit line precharge source and the bit line precharge conduction paths. The precharge source for the data buses is coupled to the data buses and at the same time access transistors normally used to couple the bit line logic voltage to the data buses are enabled, in order to cause coupling of the precharge voltage source through the data buses and the access transistors to the bit lines during a precharge interval. This both precharges and equalizes the voltage on both complementary data buses and both complementary bit lines.

REFERENCES:
patent: 4571708 (1986-02-01), Davis
patent: 4606010 (1986-08-01), Satio
patent: 4866674 (1989-09-01), Tran
patent: 4962326 (1990-10-01), Parkinson
patent: 5091885 (1992-02-01), Ohsawa

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