Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-02-11
2001-03-27
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S207000
Reexamination Certificate
active
06208575
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memories, and particularly to architecture and organization of a dynamic random-access memory array and associated supporting circuitry for its high-speed reading and writing.
2. Description of Related Art
Semiconductor random-access memory devices or sub-systems using arrays of dynamic memory cells (e.g., 1-transistor/1-capacitor (1T/1C) cells) have consistently provided greater density and lower cost per bit than those using static memory cells (e.g., 6-transistor (6T) cells, or 4-transistor/2-resistor (4T/2R) cells). However, such dynamic random-access memory arrays have historically also been lower in performance when compared to static random-access memory arrays. Consequently, system designers have typically chosen dynamic memory arrays (e.g., commercially available dynamic random access memories, or DRAMs) when high density and low cost are required, such as for CPU main memory applications. Conversely, designers have typically chosen static memory arrays when the highest possible performance is required, such as for cache memory and high speed buffer applications. Examples of static memory array devices or sub-systems include commercially available static random access memories (SRAMs) and CPU-resident on-board cache memory sub-systems.
The reasons often cited for the lower performance of dynamic memory arrays include the destructive sensing of all memory cells common to the addressed word line (encountered in virtually all dynamic memory arrays) and the consequential need to restore data back into each sensed memory cell during the active cycle, the need to equilibrate bit lines and various other differential nodes and to precharge various circuit nodes between active cycles, and the requirement for periodic refreshing of all dynamic memory cells.
In many integrated circuit devices, internal circuitry frequently operates using a single positive power supply voltage, VDD, and the reference voltage VSS (i.e., “ground”). The bit lines of a dynamic memory array are frequently equilibrated to a voltage near one-half of the power supply voltage (i.e., VDD/2 equilibration), and bit line sense amplifiers are implemented using a full CMOS cross-coupled latch. Such a CMOS latch includes a cross-coupled N-channel pair of transistors (i.e., the NMOS sense amplifier) and the cross-coupled P-channel pair of transistors (i.e., the PMOS sense amplifier). To sense the signal on a pair of bit lines, both the NMOS sense amplifier and the PMOS sense amplifier are usually enabled at substantially the same time. The NMOS sense amplifier drives the bit line having a lower voltage toward VSS, while the PMOS sense amplifier drives the bit line having a higher voltage toward VDD. After the lower bit line substantially reaches VSS and the higher bit line substantially reaches VDD, both the NMOS sense amplifier and the PMOS sense amplifier are usually disabled (along with the selected word line).
It usually takes longer to sense and restore a high-going bit line due to the inherently slower PMOS transistors compared to NMOS, as well as the greater difficulty in writing a high voltage into an NMOS array due to the significant decrease in the gate-to-source voltage at high cell (source) voltage and the apparent increase of threshold voltage resulting from increased source-to-body back-bias voltage (i.e., body effect) of memory cell access transistors and array select transistors. Moreover, as the VDD voltage has decreased in recent years to an ever lower magnitude, there is even less “turn-on” voltage (i.e., gate-to-source voltage minus the threshold voltage) for the PMOS transistors within the PMOS sense amplifier. The time required for the PMOS sense and restore function to drive the high-going bit line to a predetermined voltage is a significant portion of an active cycle. Further improvements in dynamic memory array performance, including PMOS sense and restore, are desired.
SUMMARY OF THE INVENTION
In an exemplary integrated circuit incorporating a dynamic memory array, bit line sense amplifiers are implemented using a full CMOS cross-coupled latch. Most internal circuitry, including the bit line sense amplifiers, operates using a single positive power supply voltage, VDD, and the reference voltage VSS (i.e., “ground”). To sense the signal on a pair of bit lines, both the NMOS sense amplifier and the PMOS sense amplifier are preferably enabled at substantially the same time. If enabled for a long time, the lower bit line substantially reaches VSS and the higher bit line would be driven substantially all the way to VDD. However, the PMOS sensing is preferably terminated before the higher bit line substantially reaches the full VDD voltage. This allows the bit line to quickly be driven to a high level without having to wait for the “exponential tail” if it were driven substantially all the way to VDD (e.g., four to five time constants). The internal sense amplifier nodes and the near end of the bit lines are actually driven above and overshoot the final high bit line “restore” level (e.g., 2.0 volts for a device operating at a VDD of 2.5 volts) before the PMOS sensing is terminated, whereas the far end of the high bit lines have not yet reached the final high bit line “restore” level when the PMOS sensing is terminated. Then, after the PMOS sensing is terminated, charge sharing continues between the near end and far end of the bit lines, thus speeding up the far end reaching the final high bit line “restore” level because the effective time constant of a resistive bit line is cut in half.
Since the word line and array select lines are left high for some time even after the PMOS sense amplifier is turned off, charge sharing between the sense amplifier nodes, the near and far ends of the bit lines, and the memory cell storage node itself contribute to determining the final high restore level which is “written” back into the selected memory cell. When compared to having a full VDD level on a high bit line, the relatively low final “high” bit line voltage (e.g., 2.0 volts) transfers into the selected memory cell more quickly due to the higher gate-to-source voltage of the memory cell access transistor.
The NMOS sensing is preferably continued, even after the PMOS sensing has stopped, to more adequately drive the bit line having the lower voltage (the “low-going” bit line) to a substantially full VSS level. This ensures that, if the selected memory cell happens to be coupled to the low-going bit line, a substantially full VSS level is restored into the selected memory cell. This also ensures that all the low-going bit lines (not just those having a selected memory cell connected thereto) are fully discharged before, at the end of the cycle, the high and low bit lines share their charge to set the bit line equilibrate voltage. The selected word line (which is driven when active to a VPP voltage level typically higher than VDD) is then brought low as the NMOS sensing is terminated, after which the array block is automatically taken into precharge.
Timing circuitry is used to time the simultaneous start of both NMOS and PMOS sensing relative to the tiling of the selected word line being driven high, to time the end of PMOS sensing, and to time the simultaneous end of NMOS sensing and the selected word line being brought low. The PMOS sense timing duration may be designed to decrease as the VDD voltage increases to ensure a written high level which is substantially independent of VDD, even over process and temperature corners. For example, the timing may be set to ensure a written high level on the high bit line (and into the selected memory cell) of about 2.0 volts for a device having a VDD voltage range from 2.3 to 2.9 volts. Such a PMOS sense timing generator may be accomplished by using a dummy bit line and sense amplifier structure (activated substantially before the main sense amplifiers are activated), detecting when the PMOS sensing needs to be turned off to achieve a final high voltage of about
Dinh Son T.
Zagorin, O'Brien & Graham, L.L.P.
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