Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1999-09-08
2002-07-16
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S118000, C341S120000, C341S159000, C341S141000, C341S155000, C341S163000, C341S172000, C341S143000
Reexamination Certificate
active
06420991
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to analog to digital converter (hereinafter “ADC”) systems and, more particularly, to a method and apparatus for converting element mismatch into white noise in such systems.
BACKGROUND OF THE INVENTION
A conventional multi-bit per stage, pipelined ADC
10
is shown in FIG.
1
. Four stages
12
,
14
,
16
,
18
are shown; however, as shown by ellipsis
20
, further stages may be included. An analog input signal V
IN
is provided on line
22
to stage one
12
. A first residual signal V
RES1
is provided on line
24
from stage one
12
to stage two
14
. A second residual signal V
RES2
is provided on line
26
from stage two
14
to stage three
16
. A third residual signal V
RES3
is provided on line
28
from stage three
16
to stage four
18
. A further residual signal is provided from stage four
18
on line
30
, and so forth.
Typically, all of the stages of a pipelined ADC such as ADC
10
are the same. In
FIG. 1
, the functional components of stage two
14
are shown by way of example. Thus, referring to the blowup
15
of stage two
14
, input line
24
can be seen, which is an input to sample and hold amplifier (“SHA”)
32
. The output of SHA
32
is provided on line
34
to an m-bit analog-to-digital subconverter (ADSC)
36
, which is typically a flash ADC, and to a first input of a summing unit
38
. The output of m-bit ADSC
36
is an m-bit sub-word, which is provided on line
40
both as an output to stage two
14
and is provided as an input to m-bit digital-to-analog subconverter (DASC)
42
. The output of m-bit DASC
42
is provided on line
44
to a subtracting input to summing unit
38
. The output of summing unit
38
is provided on line
46
to a
2
m
amplifier
48
, which has a theoretical gain of
2
m
. The output of
2
m
amplifier
48
is provided on line
26
.
In operation, stage two
14
operates as follows. An analog signal is provided on line
24
to SHA
32
. SHA
32
samples the analog signal on line
24
at a succession of times and holds each such sample as a signal level on line
34
for a time sufficient to permit m-bit ADSC
36
to sense the level of the signal on line
34
and provided a digital representation thereof, as a sub-word of m-bits, on line
40
. Those m-bits are converted to an analog voltage signal by m-bit DASC
42
, and provided on line
44
. The analog signal on line
44
is subtracted from the input signal on line
34
by summing unit
38
, and the difference signal is provided on line
46
to amplifier
48
, where it is amplified by a factor of 2
m
. The difference signal on line
46
represents the negative of the error made by the m-bit ADSC
36
. Theoretically, that error signal represents the inaccuracy of the m-bit representation of the analog signal on line
24
due to the limited number of bits. That error signal, amplified by 2
m
, is input to the following stage of the pipeline via line
26
, where a similar set of operations is performed.
After the signal propagates through n stages, a digital sample of the input signal V
IN
is obtained. Each of the sub-word bit lines provided at the output of the respective stage's ADSC, e.g., bit lines
40
from ADSC
36
, contributes to the overall digital word which is the digital representation provided by ADC
10
of the sampled signal V
IN
. The sub-word bit lines are concatenated to form this word. A new word is generated for each time period for which a sample is taken in the sample and hold amplifiers, e.g., SHA
32
.
In a conventional pipelined ADC, there are three main error sources. The first is the A/D subconverter linearity in the form of comparator offsets. Provided that the DASC and the interstage gain are perfect, this error can typically be removed by using digital error correction. The remaining two error sources are the D/A subconverter and the interstage gain error, both of which occur if the capacitors are not perfectly matched.
In &Sgr;-&Dgr; ADCs, capacitor mismatch results in DASC errors only. This DASC error can be reduced by using a number of dynamic element matching (“DEM”) techniques previously proposed for linearizing the DASC in multi-bit &Sgr;-&Dgr; ADCs. Examples of such techniques are described in L. R. Carley, “Noise Shaping Coder Typology for 15-bit Converters,” IEEE
J. Solid-State Circuits,
S. C. 24 No. 2, pp. 267-273, April 1989; B. H. Leung and S. Sutarja, “Multibit &Sgr;-&Dgr;A/D Converter Incorporating a Novel Class of Dynamic Element Matching Techniques,” IEEE
Trans. Circuits and Syst. II,
Vol. 39, No. 1, pp. 35-51, January 1992; R. T. Baird and T. Fiez, “Improved &Sgr;-&Dgr; DAC Linearity Using Data Weighted Averaging,”
Proc.
1995
IEEE Int. Symp. Circuits Sys.,
Vol. 1, pp. 13-16, May 1995; and R. Adams and T. Kuan, “Data-Directed Scrambler for Multi-Bit Noise Shaping D/A Converters,” U.S. Pat. No. 5,404,142, Assigned to Analog Devices, Inc., Apr. 4, 1995. By using a time varying combination of elements to represent the given DASC output level, the element mismatch errors are averaged out over time, thereby linearizing the DASC.
In a pipelined ADC, capacitor mismatch results in both DASC and interstage gain error. Direct application of existing DEM techniques to pipelined ADCs is not very effective since the interstage gain error can still degrade the overall linearity of the pipeline significantly. Therefore, it is an object of the invention to provide a solution to the problem of interstage gain error in multi-bit per stage pipelined ADCs. It is also an object of the invention to provide a solution to the problem of capacitor mismatch error in a DASC in an ADC, in addition to the problem of interstage gain error. It is also an object of the present invention to reduce such errors, while maintaining sufficient simplicity in the overall ADC design so as to permit a commercially viable product including such an ADC.
SUMMARY OF THE INVENTION
The present invention provides a method for practice in a pipelined analog to digital converter of the type for converting an analog signal to a sequence of digital words, each such word representing a value of the analog signal at a sample time in a succession of sample times, and having a plurality of pipelined stages, a first stage receiving the analog signal and the other stages receiving a residue signal from a preceding stage, each stage outputting a digital value comprising one or more bits of the word, and each stage having an input port for receiving an input signal, for sampling the input signal at each of the succession of sample times and providing a residue signal having a level corresponding to the level of the input signal, minus a level corresponding to the digital value, at each of the succession of sample times. Each stage includes a plurality of capacitors, and an amplifier, and has an input port and an output port. The method converts an analog signal to a sequence of digital words, while converting capacitor mismatch in the stages of the ADC into white noise. In the method, for each of one or more of the pipelined stages, first, the plurality of capacitors is coupled at a sample time between the stage input port and ground. Second, during an amplifying period following the sample time, one or more of the plurality of capacitors are coupled between a reference voltage and the input port of the amplifier, while the remainder of the plurality of capacitors are coupled between the input port of the amplifier and the output port of the amplifier, such that different ones of the plurality of capacitors are selected, according to a predetermined procedure uncorrelated with the analog signal, for coupling between the stage input port and ground.
These and other features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.
REFERENCES:
patent: 5006854 (1991-04-01), White et al.
patent: 5404142 (1995-04-01), Adams et al.
patent: 5412387 (1995-05-01), Vincelette et al.
patent: 5416485 (1995-05-01),
Brady III W. James
Mai Lam T.
Moore J. Dennis
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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