Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2001-10-09
2002-07-09
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S205000, C365S207000
Reexamination Certificate
active
06418064
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a sense amplifier output control circuit.
2. Description of the Prior Art
FIG. 1
is a schematic diagram of a conventional sense amplifier and sense amplifier output control circuit. The sense amplifier
11
compares an input signal IN with a reference signal REF and generates a sense-amplifier-output (SAOUT) signal in response to a sense-amplifier-enable-bar (SAENb) signal. A first NMOS transistor N
11
transfers the SAOUT signal to a latch circuit
12
in response to a latch-enable (LATCHEN) signal. The latch circuit
12
comprises three inverters I
11
, I
12
and I
13
. The SAOUT signal, transferred to the latch circuit
12
through the first NMOS transistor N
11
, is delayed by the first inverter I
11
and the second inverter I
12
for a predetermined time. The delayed SAOUT signal is inverted by the third inverter I
13
. The output signal from the latch circuit
12
is transferred to the output terminal OUT through a second NMOS transistor N
12
driven by an output-enable (OUTEN) signal. The OUTEN signal is inverted by a fourth inverter I
14
and is inputted to a third NMOS transistor N
13
coupling the output terminal OUT and a ground voltage potential Vss, in order to control the potential of the output terminal OUT.
The conventional driving method of the sense amplifier output control circuit is described in conjunction with
FIGS. 2A
to
2
C showing the output waveforms of the signals identified above.
The LATCHEN signal is generated in expectation of the output time of the SAOUT signal. The first NMOS transistor N
11
is driven by the LATCHEN signal, and the SAOUT signal is stored in the latch circuit
12
. Then, the second NMOS transistor N
12
is driven by the OUTEN signal and signals are transferred from the latch circuit
12
to the output terminal OUT. If the level of the OUTEN signal is low, the OUTEN signal is inverted to the high level through the fourth inverter I
14
and the third NMOS transistor N
13
is turned on by the inverted OUTEN signal in order to fix the output terminal OUT to the low level.
It is important to set the time for latching the SAOUT signal during the above-mentioned operation. As shown in
FIG. 2A
, it is possible to obtain normal data at the output terminal OUT, if the levels of the LATCHEN signal and the OUTEN signal are high, and the SAOUT signal is outputted correctly. However, as shown in
FIG. 2B
, if the SAOUT signal is generated earlier than the LATCHEN signal, then the signals are outputted to the output terminal OUT only when the supply of the LATCHEN signal is ended and the high level OUTEN signal is supplied.
Further, as shown in
FIG. 2C
, if the SAOUT signal is outputted after the generation of the LATCHEN signal, then the wrong SAOUT signal corresponding to- the high level LATCEN signal is outputted to the output terminal OUT.
As mentioned above, the data output speed depends on the generation time of the LATCHEN signal, and the wrong data may be outputted to the output terminal OUT, if the LATCHEN signal is generated earlier than the SAOUT signal. In order to solve this problem, the SAOUT signal is directly transferred to data output terminal OUT without passing the latch circuit
12
. However, in this case, if the SAOUT signal is changed in an instant by noise, the output data may be delayed by tens of nano-seconds even though the correct data is outputted again a little later, because time is needed to drive a large output driver transistor. That is, the prior art has the disadvantage of possible glitches caused by noise.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a sense amplifier output control circuit capable of outputting data from the sense amplifier without unwanted delays.
It is another object of the present invention to provide a sense amplifier output control circuit with reduced malfunction and power supply requirement.
In accordance with one aspect of the present invention, there is provided a sense amplifier output control circuit comprising a first logical operating means receiving an inverted output of the sense amplifier and a first control signal; a flip-flop means including a second logical operating means and a third logical operating means, wherein the second logical operating means receives signals from the first logical operating means and the third logical operating means, and wherein the third logical operating means receives signals from the second logical operating means and the first control signal; a fourth logical operating means receiving a signal from the flip-flop means and a second control signal; and a fifth logical operating means for inverting a signal from the fourth logical operating means, wherein an output terminal of the fifth logical operating means is connected to an input terminal of the sense amplifier.
In accordance with another aspect of the present invention, there is provided a semiconductor memory device, comprising a memory cell; a sense amplifier receiving a signal from the memory cell; a first. logical operating means for inverting a signal from the sense amplifier; a second logical operating means for non-disjunction of a signal from the first logical operating means and a first control signal; a flip-flop means receiving a signal from the second logical operating means and the first control signal; a third logical operating means for non-disjunction of a signal from the flip-flop means and a second control signal; and a fourth logical operating means for inverting a signal from the third logical operating means, wherein an output terminal of the fourth logical operating means is connected to an input terminal of the sense amplifier.
REFERENCES:
patent: 6009020 (1999-12-01), Nagata
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Lam David
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