Dynamic data re-programmable PLA

Details Dynamic data re-programmable PLA Dynamic data re-programmable PLA

1983-01-11

1985-06-18

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, 365221, 34082527, G11C 1300

Patent

active

045244308

ABSTRACT:
A re-programmable logic array is disclosed which has an AND array disposed for receiving n input signals on n rows of m cells per row, and an OR array providing k output lines on k rows of m cells per row. The AND and OR arrays are coupled together by m term lines. Each of the rows of the AND and OR arrays include shift register means of m charge storage elements having an input terminal coupled to the first of the m charge storage elements and an output terminal coupled to the mth one of the m charge storage elements. Multiplexors are coupled to each of the rows of both the AND and OR arrays to select between a programming operation and a recirculating refresh operation.

REFERENCES:
patent: 4422160 (1983-12-01), Watanabe

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