Dynamic circuit with slow mux input

Details Dynamic circuit with slow mux input Dynamic circuit with slow mux input

2011-07-19

2011-07-19

Chang, Daniel D (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S093000, C327S200000

Reexamination Certificate

active

07982503

ABSTRACT:
A logic circuit includes a control circuit including a first logic gate to receive a selection signal and a first input signal and to output a pulse control signal and a second logic gate to receive the pulse control signal, a clock signal, and a delayed clock signal and to output a pulse signal, and a multiplexing logic circuit to receive the selection signal and the pulse signal from the control circuit, to receive at least one second, static input signal, and to output a signal corresponding to one of the first input signal and the second, static input signal based on the state of the selection signal.

REFERENCES:
patent: 5917355 (1999-06-01), Klass
patent: 6448829 (2002-09-01), Saraf
patent: 11-068549 (1999-03-01), None

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