Dynamic access memory equalizer circuits and methods therefor

Details Dynamic access memory equalizer circuits and methods therefor Dynamic access memory equalizer circuits and methods therefor

1997-06-30

1999-02-23

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Precharge

365 63, 257390, 257401, 257412, G11C 700

Patent

active

058751386

ABSTRACT:
An equalizer circuit for precharging a pair of bit lines in a dynamic random access memory circuit. The equalizer circuit includes a substantially T-shaped polysilicon gate portion oriented at an angle relative to the pair of bit lines. The angle is an angle other than an integer multiple of 90.degree.. The substantially T-shaped polysilicon gate portion includes first polysilicon area for implementing a gate of a first switch of the equalizer circuit. The first switch is coupled to a first bit line of the pair of bit lines and a second bit line of the pair of bit lines. The substantially T-shaped polysilicon gate portion also includes a second polysilicon area for implementing a gate of a second switch of the equalizer circuit. The second switch is coupled to the first bit line of the pair of bit lines and a precharge voltage source. The substantially T-shaped polysilicon gate portion further includes a third polysilicon area for implementing a gate of a third switch of the equalizer circuit. The third switch is coupled to the second bit line of the pair of bit lines and the precharge voltage source.

REFERENCES:
patent: 5506805 (1996-04-01), Hirose et al.
patent: 5594701 (1997-01-01), Asaka et al.

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