Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2005-12-30
2009-08-18
Lee, Thomas (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S500000, C713S600000
Reexamination Certificate
active
07577861
ABSTRACT:
A method and apparatus is described herein for serializing input data streams into an output data stream. A first and second input data stream are sampled upon rising edges of a first and second clocking signal, respectively, to reduce jitter from dependence on the falling edges of the clocking signals. The second clocking signal is 180 degrees out of phase with the first clocking signal to sample the first input data stream in the first unit interval of an output data stream and the second input data stream in the second unit interval of the output data stream. Consequently, a serialized output data stream is driven at twice the frequency of both the first and the second input data streams, including logical information from the first and second input data streams every period of the output data stream.
REFERENCES:
patent: 6043682 (2000-03-01), Dabral et al.
patent: 6819145 (2004-11-01), Swartz et al.
patent: 6937173 (2005-08-01), Kim
patent: 7133484 (2006-11-01), Lin
patent: 7243173 (2007-07-01), Campbell
patent: 2005/0212561 (2005-09-01), Levin
Badrinarayanan Sriram
Levin Alexander
Matthews Chris D.
Intel Corporation
Lee Thomas
McAbee David P.
Stoynov Stefan
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