Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2007-04-17
2007-04-17
Trujillo, James K. (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S400000, C713S500000, C713S501000, C327S158000, C327S159000, C365S233100
Reexamination Certificate
active
11351277
ABSTRACT:
A technique for compensating for duty cycle distortion in an output data signal generated by a synchronous dynamic random access memory device (SDRAM) is provided. The output latch of the SDRAM is driven by an output clock signal generated by a delay lock loop (DLL). The output clock signal is phase-shifted relative to a reference clock signal received by the DLL such that the data removed from the output latch is synchronous with the reference clock signal. Further the duty cycle of the output clock signal is adjusted in a phase inverse relationship to the duty cycle distortion introduced by the output latch. As a result, the output data signal has reduced duty cycle distortion.
REFERENCES:
patent: 5614855 (1997-03-01), Lee
patent: 6003118 (1999-12-01), Chen
patent: 6016282 (2000-01-01), Keeth
patent: 6321282 (2001-11-01), Horowitz et al.
patent: 6323705 (2001-11-01), Shieh et al.
patent: 6452432 (2002-09-01), Kim
patent: 6580305 (2003-06-01), Liu et al.
patent: 6584021 (2003-06-01), Heyne et al.
patent: 6718477 (2004-04-01), Plants et al.
patent: 6763477 (2004-07-01), McGee
patent: 2001/0029566 (2001-10-01), Shin
patent: 411186903 (1999-07-01), None
Hamamoto, T; Kawasaki, S.; Furutani, K.; Yasuda, K.; Konishi, Y.; A skew and jitter suppressed DLL architecture for high frequency DDR SDRAMs, VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on, Jun. 15-17, 2000, pp. 76 and 77.
Johnson James B.
Lin Feng D.
Fletcher Yoder PC
Micro)n Technology, Inc.
Trujillo James K.
LandOfFree
Duty cycle distortion compensation for the data output of a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Duty cycle distortion compensation for the data output of a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Duty cycle distortion compensation for the data output of a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3783094