Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2006-04-11
2006-04-11
Browne, Lynne H. (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S400000, C713S500000, C713S501000, C327S158000, C327S159000, C365S233100
Reexamination Certificate
active
07028208
ABSTRACT:
A technique for compensating for duty cycle distortion in an output data signal generated by a synchronous dynamic random access memory device (SDRAM) is provided. The output latch of the SDRAM is driven by an output clock signal generated by a delay lock loop (DLL). The output clock signal is phase-shifted relative to a reference clock signal received by the DLL such that the data removed from the output latch is synchronous with the reference clock signal. Further the duty cycle of the output clock signal is adjusted in a phase inverse relationship to the duty cycle distortion introduced by the output latch. As a result, the output data signal has reduced duty cycle distortion.
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Johnson James B.
Lin Feng D.
Browne Lynne H.
Micro)n Technology, Inc.
Trujillo James K.
Yoder Fletcher
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