Dummy structures that protect circuit elements during polishing

Details Dummy structures that protect circuit elements during polishing Dummy structures that protect circuit elements during polishing

2002-06-06

2004-03-02

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

28, 28, 28, 28

Reexamination Certificate

active

06700143

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to fabrication of integrated circuits, and more particularly to use of polishing processes, such as chemical mechanical polishing (CMP), in the fabrication of integrated circuits.
CMP is widely used to planarize the top surface of a dielectric layer before the dielectric is patterned or subsequent layers are deposited. Planarization is desirable because it relaxes the depth of focus requirements for photolithographic equipment used to pattern the dielectric layer or the overlying layers. If the top surface of the dielectric is planar, greater variation of the depth of focus can be tolerated. This is especially important if the photolithographic equipment has to create small geometries.
CMP is widely used for planarization because CMP is fast and does not require high temperatures.
SUMMARY
Chemical mechanical polishing of a dielectric layer typically stops on a harder layer underlying the dielectric layer. For example, CMP of silicon dioxide can stop on silicon nitride deposited before the silicon dioxide. See U.S. Pat. No. 5,909,628, issued Jun. 1, 1999, entitled “REDUCING NON-UNIFORMITY IN A REFILL LAYER THICKNESS FOR A SEMICONDUCTOR DEVICE”.
Some embodiments of the present invention relate to integrated circuits which have circuit elements formed from different conductive or semiconductor layers. For example, an integrated circuit may have transistor gates formed from different polysilicon layers. A dielectric overlies these polysilicon layers, and is polished by CMP. A harder layer is formed over the polysilicon layers underneath the dielectric layer. CMP stops on the harder layer. For example, the dielectric polished by CMP can be silicon dioxide, and the harder layer can be silicon nitride. The harder layer is patterned to form protective features over one of the polysilicon layers (“first polysilicon layer”) but not over the other one of the polysilicon layers (“second polysilicon layer”). Dummy structures are formed from the first polysilicon layer adjacent to the transistor gates formed from the second polysilicon layer. Dummy structures include portions of the first polysilicon layer and portions of the harder layer. The harder layer portions protect the transistor gates formed from the second polysilicon layer from being exposed during the polishing.
In some embodiments, the first and second polysilicon layers also provide capacitor plates in the integrated circuit. In some embodiments, the circuit processes analog signals and, possibly, also digital signals.
The invention is not limited to transistors gates or capacitor plates. The invention is not limited to polysilicon, silicon dioxide, silicon nitride, or any other particular materials. In some embodiments, a method for fabricating an integrated circuit comprises: forming a first layer over a semiconductor substrate, the first layer providing at least a portion of a first circuit element and at least a portion of a dummy element; forming a second layer over the semiconductor substrate, the second layer providing at least a portion of a second circuit element; forming a protective feature from a third layer over the first circuit element and the dummy element but not over the second circuit element; forming a dielectric layer over the first, second and third layers; and polishing the dielectric layer by a polishing process that stops on the third layer, such that the protective feature over the dummy element protects the second element during the polishing process.
Other features and advantages of the invention are described below.


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