Dummy pattern design for reducing device performance drift

Details Dummy pattern design for reducing device performance drift Dummy pattern design for reducing device performance drift

2011-06-07

2011-06-07

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Design of semiconductor mask or reticle

Layout generation

C716S119000, C716S126000, C716S132000

Reexamination Certificate

active

07958465

ABSTRACT:
A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip.

REFERENCES:
patent: 5278105 (1994-01-01), Eden et al.
patent: 6281049 (2001-08-01), Lee
patent: 6284626 (2001-09-01), Kim
patent: 6984564 (2006-01-01), Huang et al.
patent: 7119404 (2006-10-01), Chang et al.
patent: 7164163 (2007-01-01), Chen et al.
patent: 7232730 (2007-06-01), Chen et al.
patent: 7484198 (2009-01-01), Lin et al.
patent: 7600207 (2009-10-01), Moroz et al.
patent: 7767515 (2010-08-01), Moroz et al.
patent: 2007/0204250 (2007-08-01), Moroz et al.
patent: 2009/0007043 (2009-01-01), Lin et al.
patent: 2009/0313595 (2009-12-01), Moroz et al.
patent: 2001-332706 (2001-11-01), None
Hall et al., “Impact of Via Interactions and Metal Slotting on Stress Induced Voiding”, IEEE International Reliability Physics Symposium, Apr. 27 to May 1, 2008, pp. 392-398.
Topaloglu, “Standard Cell and Custom Circuit Optimization using Dummy Diffusions Through STI Width Stress Effect Utilization”, IEEE Custom Integrated Circuits Conference, Sep. 16-19, 2007, pp. 619-622.

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