Dual stage DRAM memory equalization

Details Dual stage DRAM memory equalization Dual stage DRAM memory equalization

2006-05-02

2006-05-02

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S205000, C365S190000, C365S194000

Reexamination Certificate

active

07038958

ABSTRACT:
A memory device equilibrates voltages in a bit line pair to a reduced voltage level. The reduced equilibrate voltage level can be achieved by separating the conventional equilibrate process so that the positive portion and the negative portion of the sense amplifier are equilibrated at different times. Bit line equilibration can be associated with either the equilibrate step associated with the positive portion of the sense amplifier or the equilibrate step associated with the negative portion of the sense amplifier.

REFERENCES:
patent: 5646900 (1997-07-01), Tsukude et al.
patent: 5881005 (1999-03-01), Otori et al.

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