Dual spacer method of forming CMOS transistors with...

Details Dual spacer method of forming CMOS transistors with... Dual spacer method of forming CMOS transistors with...

1999-08-24

2001-10-23

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000

Reexamination Certificate

active

06306702

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method of forming highly dense, very small integrated circuits semi-conductor devices. More particularly, this invention relates to a method for manufacturing an integrated circuit containing both NMOS and PMOS field effect transistors having substantially the same sub-micrometer gate lengths.
2. Description of the Related Art
In order to enable cost-efficient commercial production of integrated circuits which exhibit narrow line widths in the range of about 1 micrometer or less, it is necessary to use optical lithography techniques and to avoid the more expensive and complex techniques such as electron beam or X-ray lithography. In this connection, there has been significant efforts to develop processes for making submicrometer channel length field effect transistors with a high degree of channel length control. Examples of such work are described in “A New Edge-defined Approach for Sub-micrometer MOSFET Fabrication” by W. R. Hunter et al., IEEE Electron Device Letters, Vol. EDL-2 No. 1, January 1981, pp. 4-6, “Sub-micrometer Polysilicon Gate CMOS/SOS Technology” by A. C. Ipri et al. published in IEEE Transactions on Electron Devices, Vol. ED-27, No. 7, July 1980, pp. 1275-1279 and “A Novel Sub-micron Fabrication Technique” by T. N. Jackson et al. published in IEDM 1979 Conference Volume, pp. 58-61.
The W. R. Hunter document relies on the reactive ion etching technique to form a sidewall silicon dioxide. The Ipri et al. document utilizes a technique involving lateral diffusion of boron. The T. N. Jackson et al. method uses the plating of a metal on the edge of a conventionally patterned metal layer. Other short channel field effect transistor devices are illustrated in the W. E. Armstrong U.S. Pat. No. 4,062,699; J. Goel U.S. Pat. No. 4,145,459 and J. H. Scott, Jr. U.S. Pat. No. 4,201,603.
The Armstrong patent utilizes an ion implantation and diffusion process to narrow the channel length of his MOSFET. On the other hand, the Goel patent utilizes a process sequence that involves forming a recess in a portion of the semiconductor body and plating a metal film on each side of the recess until the spacing between the metal films across the recess is equal to desired length of the gate. The Scott, Jr. patent controllably dopes an edge of a polysilicon layer and then removes the undoped polysilicon by etching with an etchant which does not etch the doped polysilicon region. The above mentioned U.S. Pat. Nos. 4,209,349 and 4,209,350 also show processes for making sub-micrometer channel length devices with highly doped source/drain regions.
A particularly effective MOSFET configuration allowing high densities and performance is described in “A New Short Channel MOS FET with Lightly Doped Drain” by Saito et al. in Denshi Tsushin Rengo Taikai (Japanese), April 1978, page 2-20. The LDD (lightly doped drain) N channel MOS FET includes, in addition to the channel separating implanted N+ source/drain regions, the sub-micrometer diffused N- regions, which increases the channel breakdown voltage or snap-back voltage and reduces device drain junction electron impact ionization (and thus, hot electron emission) by spreading the high electric field at the drain pinch-off region into the N− region. This allows either an increase in power supply voltage or reduction in channel length at a given voltage to achieve performance enhancement. An improved process for making such a device is given in U.S. Pat. No. 4,366,613 S. Ogura and P. J. Tsang and entitled “Method of Fabricating High Speed High Density MOS Dynamic RAM With Lightly Doped Drain”, in which the N− LDD region of the device is formed by a controlled N− ion implantation and forming sub-micrometer wide SiO
2
sidewall spacers abutting the gate.
In the above-mentioned patent to Ogura the formation of oxide sidewalls enables the prior formation of shallow lightly doped regions followed by subsequent implantation to form deeper, heavily doped contiguous regions. This reference further stresses the advantage of allowing ready fabrication of a self-aligned capacitance storage node. This is implemented by implanting a P-type impurity, e.g., boron, between a selected gate electrode and an adjacent insulation region, subsequent to reactive ion etching but prior to the formation of the capacitor plate and the N+ implant. Further merit is disclosed as residing in the fact that the LDD regions of the device allows the high electric field at the drain pinch-off region to be spread, thereby increasing the channel breakdown voltage or snap-back voltage and reducing hot electron emission for enhanced performance. The use of oxide sidewall spacers also protects the polysilicon gate from oxidation and prevents the formation of a reversed “bird's beak” that would normally form along two sides of the polysilicon gate during source/drain oxidation.
Nevertheless, it is difficult to form N
−
and P
−
channel transistors which have the same gate length (Leff) due to the large difference in diffusion and activation requirements of commonly used dopants. That is to say, in conventional arrangements wherein a combination of As and BF
2
is used for example, the activation temperature of As is higher than that required for BF
2
. As a result, during annealing, the respective diffusions start at different times and, therefore, by the time the appropriate amount of diffusion of one is achieved, the other tends to be either excessive or insufficient.
Accordingly, there exists a need for a technique via which both NMOS and PMOS transistors can be formed with substantially the same gate length.
SUMMARY OF THE INVENTION
The present invention is based on the use of impurities of dopants which require different activation temperatures to form the source and drains of NMOS and PMOS transistors. This combination of impurities or dopants which exhibit different activation temperatures, coupled with the use of double spacers, enables the different dopants to be selectively deposited and selectively diffused in a manner that enables the formation of CMOS transistors with substantially the same gate length.
In an embodiment of the present invention, the dopants are arsenic (As) and boron difluoride (BF
2
). The activation temperatures of these dopants are different, thereby allowing the use of different activation temperatures to control the amount of diffusion during fabrication. The use of a double insulating sidewall spacers, in combination with staged doping, allows diffusion of the dopants in such a manner to obtain substantially the same gate lengths of the CMOS transistors.
More specifically, an aspect of the invention resides in a method of forming N and P-type transistors having substantially the same gate lengths. This method features the steps of: (a) forming polysilicon gates for both NMOS and PMOS transistors on a substrate. (b) ion implanting an N-type impurity to form lightly doped source/drain extension implants of the first transistor; (c) forming first insulating sidewall spacers, having a first thickness, on the side surfaces of each of the first and second gates; (d) ion implanting a P-type impurity to form lightly doped source/drain extension implants of the second transistor; (e) forming second insulating sidewall spacers, typically thicker than first sidewall spacers; (f) ion implanting an N-type impurity to form moderately or heavily doped source/drain implants of the first transistor; (g) activation annealing at a first temperature to form moderately or heavily doped source/drain regions of the first transistor; (h) ion implanting a P-type impurity to form moderately or heavily doped source/drain implants of the second transistor; and (i) activation annealing at a second temperature, which is lower than the first temperature, to form moderately or heavily doped source/drain regions of the second transistor.
The N-type impurity can be As and the first portion of the substrate a P-doped or a P-well in a N-doped s

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