Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-01-03
2006-01-03
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000, C257S365000, C257S366000
Reexamination Certificate
active
06982464
ABSTRACT:
A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.
REFERENCES:
patent: 6611029 (2003-08-01), Ahmed et al.
patent: 6642090 (2003-11-01), Fried et al.
patent: 6645797 (2003-11-01), Buynoski et al.
patent: 6689650 (2004-02-01), Gambino et al.
patent: 6756643 (2004-06-01), Achuthan et al.
patent: 2001/0036731 (2001-11-01), Muller et al.
patent: 2002/0130354 (2002-09-01), Sekigawa et al.
patent: 2002/0177263 (2002-11-01), Hanafi et al.
patent: 2003/0057486 (2003-03-01), Gambino et al.
Digh Hisamoto et al.: “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al.: “Sub-20nm CMOS Fin FET Technologies,” 0-7803-5410-9/99 IEEE, Mar. 2001, 4 pages.
Xuejue Huang et al.: “Sub-50 nm P-Channel Fin FET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Yang-Kyu Choi et al.: “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.
Xuejue Huang et al.: “Sub 50-nm FinFET: PMOS,” 0-7803-7050-3/01 IEEE, Sep. 1999 4 pages.
Achuthan Krishnashree
Ahmed Shibly S.
Wang Haihong
Yu Bin
Advanced Micro Devices , Inc.
Harrity & Snyder LLP
Wojciechowicz Edward
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