Variable size First In First Out (FIFO) memory with head and...

Details Variable size First In First Out (FIFO) memory with head and... Variable size First In First Out (FIFO) memory with head and...

2006-01-17

2006-01-17

Phan, Man U. (Department: 2665)

Multiplex communications

Pathfinding or routing

Store and forward

C710S029000

Reexamination Certificate

active

06987775

ABSTRACT:
A variable size first in first out (FIFO) memory is provided. The variable size FIFO memory may include head and tail FIFO memories operating at a very high data rate and an off chip buffer memory. The off chip buffer memory may be, for example, of a dynamic RAM type. The off chip buffer memory may temporarily store data packets when both head and tail FIFO memories are full. Data blocks of each of the memories may be the same size for efficient transfer of data. After a sudden data burst which causes memory overflow ceases, the head and tail FIFO memories return to their initial functions with the head FIFO memory directly receiving high speed data and transmitting it to various switching element and the tail FIFO memory storing temporary overflows of data from the head FIFO memory.

REFERENCES:
patent: 4394725 (1983-07-01), Bienvenu et al.
patent: 4704606 (1987-11-01), Hasley
patent: 4754451 (1988-06-01), Eng et al.
patent: 5550823 (1996-08-01), Irie
patent: 5610914 (1997-03-01), Yamada
patent: 5659713 (1997-08-01), Goodwin
patent: 5845145 (1998-12-01), James
patent: 5905911 (1999-05-01), Shimizu
patent: 5961626 (1999-10-01), Harrison
patent: 5982749 (1999-11-01), Daniel et al.
patent: 6067408 (2000-05-01), Runaldue et al.
patent: 6122674 (2000-09-01), Olnowich
patent: 6172927 (2001-01-01), Taylor
patent: 6292878 (2001-09-01), Morioka
patent: 6389489 (2002-05-01), Stone
patent: 6442674 (2002-08-01), Lee et al.
patent: 6460120 (2002-10-01), Bass
patent: 6487171 (2002-11-01), Honig
patent: 6493347 (2002-12-01), Sindhu
patent: 6510138 (2003-01-01), Pannell
patent: 6557053 (2003-04-01), Bass et al.
patent: 6570876 (2003-05-01), Aimoto
patent: 6574194 (2003-06-01), Sun et al.
patent: 6611527 (2003-08-01), Moriwaki
patent: 6687768 (2004-02-01), Horikomi
patent: 6708262 (2004-03-01), Manning
patent: 6795870 (2004-09-01), Bass
patent: 2002/0054602 (2002-05-01), Takahashi
patent: 2002/0099855 (2002-07-01), Bass
patent: 2002/0122386 (2002-09-01), Calvignac
PetaSwitch Solutions, Inc., The Pisces Chipset, Product Brief, 2001, http://www.peta-switch.com/products/product—brief.htm.
PetaSwitch Solutions, Inc., PetaSwitch Solutions Announces Raising $4 Million in First Round Financing, Press Release, 2001, http://peta-switch.com
ewsroom/press—releases.htm.
Gupta, Scheduling in Input Queued Switches: A Survey, Jun. 1996, Department of Computer Science, Stanford University, California.
Schoenen, et al., Distributed Cell Scheduling Algorithms for Virtual-Output-Queued Switches, Dec. 1999, pp. 1211-1215, vol. 1, GLOBECOM, IEEE Global Telecommunications Conference.
Fahmy, A Survey of ATM Switching Techniques, Aug. 14, 2001, Department of Computer and Information Science, The Ohio State University.

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