Dual Si-Ge polysilicon gate with different Ge concentrations...

Details Dual Si-Ge polysilicon gate with different Ge concentrations... Dual Si-Ge polysilicon gate with different Ge concentrations...

2002-10-08

2004-03-23

Pert, Evan (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S019000, C257S069000, C257S616000, C438S231000, C438S585000, C438S752000, C438S933000

Reexamination Certificate

active

06709912

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of fabricating dual Si—Ge polysilicon gates having different Ge concentrations in the fabrication of integrated circuits.
(2) Description of the Prior Art
Silicon-Germanium (Si—Ge) polycrystalline gates have advantages over conventional silicon polycrystalline gates. Lee et al in “Investigation of poly-Si
1−x
Ge
x
for dual-gate CMOS technology,” IEEE EDL, p. 247, 1998 and in “Observation of reduced boron penetration and gate depletion for poly-Si0.8Ge0.2 gated PMOS devices,” IEEE EDL, p.9, 1999 have reported that polysilicon-gate depletion (PD) effect and boron penetration effect for PMOS devices is reduced with increasing Ge concentration, while NMOS devices with approximately 20% Ge concentration exhibit the least PD effect. Later, in “Enhancement of PMOS device performance with poly-SiGe gate”, IEEE EDL, p. 232, 1999, Lee et al reported that the hole's mobility for PMOS devices with Si—Ge poly is higher than those devices with Si-poly.
In “Work function of boron-doped polycrystalline Si
x
Ge
1−x
films”, IEEE EDL, p. 456, 1997, Hellberg et al reported that the work function for p
+
-doped SiGe polycrystalline film decreases as the Ge content increases. Hence, it is possible to improve the CMOS device performance by using gate work function engineering coupled with super-steep retrograde channel engineering (“High-performance deep submicron CMOS technologies with polycrystalline-SiGe gates,” Ponomarev et al, IEEE ED, p. 848, 2000) or lateral channel engineering (“A 0.13 &mgr;m poly-SiGe gate CMOS technology for low-voltage mixed-signal applications,” Ponomarev et al, IEEE ED, p. 1507, 2000)
Ponomarev et al in “Gate workfunction engineering using poly-(SiGe) for high performance 0.18 &mgr;m CMOS technology,” IEDM, p. 829, 1997, reported that a buffer poly-Si layer can be introduced on the Si—Ge poly gate to preserve the standard salicidation scheme. Uejima et al in “Highly reliable poly-SiGe/amorphous-Si gate CMOS”, IEDM, p. 60, 2000, reported that gate oxide reliability can be improved by adding a thin amorphous silicon layer prior to Si—Ge polysilicon deposition.
Since it is desirable to have about 20% and about 50% Ge for NMOS and PMOS devices, respectively, in order to achieve the optimum performance for CMOSFET's, it is desired to provide a method for forming a dual Si—Ge poly-gate CMOSFET with different Ge concentrations for NMOS and PMOS devices.
U.S. Pat. No. 6,326,252 B1 to Kim et al, U.S. Pat. No. 6,303,418 B1 to Cha et al, and U.S. Pat. No. 6,323,115 B1 to Tanabe et al disclose dual gate processes. U.S. Pat. No. 6,200,866 B1 to Ma et al shows a replacement gate process using SiGe as the dummy gate material.
SUMMARY OF THE INVENTION
Accordingly, a primary object of the invention is to provide a process for forming dual Si—Ge poly-gates in the fabrication of integrated circuits.
A further object of the invention is to provide a process for forming dual Si—Ge poly-gates having different Ge concentrations in the fabrication of integrated circuits.
Another object of the invention is to provide a process for forming dual Si—Ge poly-gates having different Ge concentrations for NMOS and PMOS devices in the fabrication of integrated circuits.
Yet another object of the invention is to provide a process for forming dual Si—Ge poly-gates having different Ge concentrations for NMOS and PMOS devices using blanket Si—Ge polysilicon deposition followed by selective Ge implantation in the PMOS region.
In accordance with the objects of the invention, a method for forming a dual Si—Ge poly-gates having different Ge concentrations is achieved. An NMOS active area and a PMOS active area are provided on a semiconductor substrate separated by an isolation region. A gate oxide layer is grown overlying the semiconductor substrate in each of the active areas. A polycrystalline silicon-germanium (Si—Ge) layer is deposited overlying the gate oxide layer wherein the polycrystalline Si—Ge layer has a first Ge concentration. The NMOS active area is blocked while the PMOS active area is exposed. Successive cycles of Ge plasma doping and laser annealing into the PMOS active area are performed to achieve a second Ge concentration higher than the first Ge concentration. The polycrystalline Si—Ge layer is patterned to form a gate in each of the active areas wherein the gate in the PMOS active area has a higher Ge concentration than the gate in the NMOS active area to complete formation of dual Si—Ge polysilicon gates with different Ge concentrations in the fabrication of an integrated circuit device.


REFERENCES:
patent: 6200866 (2001-03-01), Ma et al.
patent: 6303418 (2001-10-01), Cha et al.
patent: 6323115 (2001-11-01), Tanabe et al.
patent: 6326252 (2001-12-01), Kim et al.
patent: 6451676 (2002-09-01), Wurzer et al.
patent: 6524902 (2003-02-01), Rhee et al.
patent: 6596605 (2003-07-01), Ha et al.
patent: 2001/0015922 (2001-08-01), Ponomarev
Lee et al., “Investigation of Poly-Si1—xGexfor Dual-Gate CMOS Technology,” IEEE EDL, vol. 19, No. 7, Jul. 1998, pp. 247-249.
Wen-Chin Lee et al., “Observation of Reduced Boron Penetration and Gate Depletion for Poly-Si0.8Geo0.2Gated PMOS Devices,” IEEE-EDL, vol. 20, No. 1, Jan. 1999, pp. 9-11.
“Enhancement of PMOS Device Performance with Poly-SiGe Gate”, by Wen-Chin Lee et al.,IEEE EDL, vol. 20, No. 5, May 1999, pp. 232-234.
“Work Function of Boron-Doped Polycrystalline SixGe1—xFilms”,IEEE EDL, vol. 18, No. 9, Sep. 1997, pp. 456-458, P.-E. Hellberg et. al.
Uejima et al., “High Reliable Poly-SiGe/Amorphous-Si Gate CMOS”,IEDM2000, pp. 18.5.1-18.5.4.
“High-Performance Deep SubMicron CMOS Tch. with Polycrystalline-SiGe Gates”, by Youri V. Ponomarev et al., IEEE Trans. on Electron Devices, vol. 47, No. 4, Apr. 2000, pp. 848-855.
“A 0.13 &mgr;m Poly-SiGe Gate CMOS Tech. for Low-Voltage Mixed-Signal Applications,” IEEE Trans. on Electron Device, vol. 47, No. 7, Jul. 2000, pp. 1507-1513, Youri V. Ponomarev et al.
Ponomarev et al., “Gate-Workfunction Engineering Using Poly-(Si,Ge) for High Performance 0.18&mgr;m CMOS Technology,” 1997,IEDM, pp. 829-832.

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