Dual power bus data storage system

Details Dual power bus data storage system Dual power bus data storage system

2006-06-13

2006-06-13

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S004000, C711S112000, C711S114000, C714S005110, C714S006130

Reexamination Certificate

active

07062620

ABSTRACT:
A data storage interface for coupling data between processors and a bank of disk. The interface includes a plurality of first directors coupled to the processors and a plurality of second directors coupled to the bank of disk drives. A cache memory is coupled between the plurality of first directors and the plurality of second directors. The interface includes a pair of independent power busses. At least one of the first or second directors is coupled to the pair of independent power busses. One portion of the disk drives in the bank is connected to only a first one of the pair of power buses and a different portion of the disk drives is connected to only the other one of the pair of power buses. A power circuit includes a pair of input terminals, each one being electrically connected to a corresponding one of the pair of independent power busses. The circuit includes an output terminal. A pair of switching transistor sections is provided. The transistor switching sections is serially connected between a corresponding one of the pair of input terminals and the output terminal. A logic network is provided for operating the switching sections to prevent current passing into one of the pair of input terminals from one of the power busses from passing into the other one of the power buses. The logic section operates the switching sections to prevent current from one of the pair of power buses to the one of the input terminals connected thereto from exceeding a predetermined value, and operates the switching sections to prevent a difference between a voltage at one of the input terminals and a voltage at the other one of the input terminals from exceeding a predetermined value.

REFERENCES:
patent: 5325363 (1994-06-01), Lui
patent: 5396596 (1995-03-01), Hashemi et al.
patent: 5453765 (1995-09-01), Yamaguchi et al.
patent: 5768117 (1998-06-01), Takahashi et al.
patent: 6230217 (2001-05-01), Tuccio et al.
patent: 6230221 (2001-05-01), Mulvey et al.
patent: 6597073 (2003-07-01), Check
patent: 6742068 (2004-05-01), Gallagher et al.
patent: 2002/0026595 (2002-02-01), Saitou et al.

Affiliated with

Also associated with

Rating

Dual power bus data storage system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual power bus data storage system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual power bus data storage system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3662793