Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1998-05-22
2001-09-18
Robertson, David L. (Department: 2759)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S154000
Reexamination Certificate
active
06292873
ABSTRACT:
TECHNICAL FIELD
The present invention relates to computer random access memories and, in particular, to a dual-ported shared random access memory supporting fully independent and concurrent access from both ports without wait states.
BACKGROUND OF THE INVENTION
Dual-ported shared memory is, for efficiency reasons, an essential component in many multi-bus computer system architectures. For example,
FIG. 1
is an architecture block diagram of a high-performance Fibre Channel/SCSI-bus multiplexer that exchanges data transfer commands and data between Fibre Channel networks and SCSI buses. The high-performance Fibre Channel/SCSI-bus multiplexer includes Fibre Channel host adapters
102
and
104
, SCSI-bus adapters
106
-
109
, and an internal processor
110
that all access a dual-ported shared memory
112
via an upper Peripheral Component Interconnect (“PCI”) bus
114
and lower PCI bus
116
. Data is exchanged between Fibre Channel host adapters
102
and
104
and the SCSI-bus adapters
106
-
109
through buffers allocated from within the dual-ported shared memory
112
. Because a high-performance Fibre Channel/SCSI-bus adapter must concurrently, in both directions, transfer data at very high data transfer rates, it is vital that the dual-ported shared memory provide essentially independent channels for both reading and writing the contents of the dual-ported shared memory, and the reading and writing transfers need to transfer data at the data transfer rate provided by the upper PCI bus
114
and lower PCI bus
116
connected to the two ports.
For example,
FIG. 2
illustrates a snapshot in time of simultaneous memory accesses of the dual-ported shared memory within the high-performance Fibre Channel/SCSI-bus multiplexer. In
FIG. 2
, the contents of a memory buffer
202
within the dual-ported shared memory
204
is being read from the first port
206
at the same time that a different memory buffer
208
is being written from the second port
210
. This circumstance often arises during a double-buffered transfer of data from a mass storage device controlled by a SCSI adapter to a remote computer system reading data from the mass storage device via a Fibre Channel connection.
Currently-available dual-ported shared memory designs do not support maximally efficient data transfers to two independent ports.
FIG. 3
illustrates common deficiencies in currently-available dual-ported shared memory designs. In
FIG. 3
, a clock signal
302
for a clock driving two computer buses is shown superimposed with the data being transferred on the first computer bus
304
and the data being transferred on the second computer bus
306
. For maximal efficiency of data transfer, the dual-ported shared memory should be able to provide the contents of successive memory locations, in the case of a read operation, or receive values to be placed in successive memory locations, in the case of write operations, during each clock cycle. However, in currently-available dual-ported shared memories, the dual-ported shared memory frequently introduces wait states, which are essentially empty or lost clock cycles during which data is not transferred. For example, in the data contents for the first computer bus
304
, the dual-ported shared memory was not able to provide or accept data values during clock cycles
308
and
310
. Another commonly-occurring problem in currently-available dual-ported shared memories is overhead associated with restarting a data transfer from or to the dual-ported shared memory after the computer bus introduces wait states during the data transfer. For example, in the data transfer for the second computer bus
306
, the computer bus stops sending data, for two clock cycles, at clock cycles
312
and
314
. At clock cycle
316
, the computer bus asserts a signal line on the computer bus to indicate the ability to again receive data from the dual-ported shared memory. However, the dual-ported shared memory then incurs a latency period during clock cycles
316
and
318
and, when the dual-ported shared memory finally begins to resume data transfer, at clock cycle
320
, the dual-ported shared memory begins retransmitting data that was previously transferred in the clock cycles
322
-
325
that immediately preceded the wait cycles
312
and
314
introduced by the second computer bus.
Thus, a need has been recognized in the computer industry for a dual-ported shared memory that can provide a continuous flow of data to two different computer buses. It is desirable that such a dual-ported shared memory be able to support both read and write operations simultaneously to both computer buses without introducing wait states and without retransmitting data following a wait state introduced by either of the computer buses.
SUMMARY OF THE INVENTION
The present invention provides a high-performance, efficient dual-ported shared memory that independently provides both reading and writing data transfer operations to two different computer buses. The dual-ported shared memories implemented with 4 2-megabyte static random access memories are connected to a data multiplexer and an address multiplexer via a 64-byte bus. The data multiplexer and address multiplexer interface with two different 32-bit PCI buses. During each clock cycle, the data multiplexer can transfer a 32-bit word to, or receive a 32-bit word from, each PCI bus. During each clock cycle, the data multiplexer can transfer a 64-bit word to, or receive a 64-bit word from, the static random access memories. Thus, during each clock cycle, the data multiplexer can move 2 32-bit words between the PCI buses and the static random access memories.
The static random access memories are laid out into even and odd aligned word columns. During each clock cycle, the data multiplexer can transfer a 32-bit word to or from a memory location within the even data column, and a 32-bit word to or from a successive memory location within the odd data column. The data multiplexer alternates 64-bit transfers for each PCI bus at successive clock cycles. Thus, the data multiplexer can transfer 64-bits of data between a particular PCI bus and the static random access memories at every other clock cycle. By internally buffering data received either from the PCI bus during a write operation, or the static random access memory during a read operation, the data multiplexer can receive a 32-bit word from, or transfer a 32-bit word to, each PCI bus during each clock cycle. By internally buffering 96-bits of data for each data transfer direction between the data multiplexer and each PCI bus, the dual-ported shared memory has sufficient internal storage capacity to immediately resume data transfer following a wait state imposed by a PCI bus.
REFERENCES:
patent: 4320450 (1982-03-01), Rose et al.
patent: 4783731 (1988-11-01), Miyazaki et al.
Barsness et al., Storage Interface with Buffer, IBM Technical Disclosure Bulletin, vol. 27, No. 4A,Sep. 1984, pp. 2140-2148.
Cross Donald M.
Keaveny Thomas A.
Hewlett--Packard Company
Robertson David L.
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