Dual port semiconductor memory having random and serial access m

Details Dual port semiconductor memory having random and serial access m Dual port semiconductor memory having random and serial access m

1987-01-20

1989-08-15

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365221, 36523007, 36523005, 340800, G11C 700, G11C 800

Patent

active

048581909

ABSTRACT:
A semiconductor memory is provided in which a column decoder is used commonly for the random input and output and the serial input/output by providing both a signal path for transmitting signals in parallel to the data lines of a memory array and a latch circuit and a switch path for connecting said latch circuit and a serial input/output common data line in response to a selection signal generated by a shift register, and by feeding the output signal of a random input/output column decoder as an initial value to the individual bits of said shift register.

REFERENCES:
patent: 4402067 (1983-08-01), Moss et al.
patent: 4412313 (1983-10-01), Aekland et al.
patent: 4422160 (1983-12-01), Watanabe
patent: 4498155 (1985-02-01), Mohan Rao
patent: 4646270 (1987-02-01), Voss
patent: 4723226 (1988-02-01), McDonough et al.
Nikkei Electronics, Aug. 12, 1985, pp. 211-240.

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