Dual-port read/write RAM with single array

Details Dual-port read/write RAM with single array Dual-port read/write RAM with single array

1984-10-31

1986-11-18

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, G11C 700

Patent

active

046239901

ABSTRACT:
A single-array memory employs a novel storage cell providing dual read/write access via either an "A"-side or a "B"-side. The storage cell uses a unique circuit in which read current is borrowed during writing into the cell. Asymmetrical read/write delay circuitry is provided to avoid overwriting the contents of a storage cell during the read-to-write transition. Row-selection decoders use Schottky-clamping diodes in a way which provide an equivalent oscillation-damping capacitance at the base of the selected-row driver transistor. The single-array memory can be advantageously used as part of a single-chip VLSI four-port register file permitting simultaneous reading and/or writing of registers from any of two read ports or two write ports, respectively. Unidirectional busses connect each storage cell to each of the four ports.

REFERENCES:
patent: 4287575 (1981-09-01), Eardley et al.
patent: 4541076 (1985-09-01), Bowers et al.
J. R. Reinert et al., "A 32.times.9 ECL Dual Address Register Using an Interleaving Cell Technique", 1977 IEEE International Solid-State Circuit Conference, Feb. 16, 1977.

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