Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2005-06-14
2005-06-14
Bragdon, Reginald G. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S156000, C709S213000, C701S115000
Reexamination Certificate
active
06907503
ABSTRACT:
An apparatus for determining the validity of a data signal communicated between two microprocessors by a dual port RAM includes a sender for providing a data signal and an initialization status indicator and a dual port RAM in communication with the sender for receiving the data signal and the initialization status indicator. The RAM has a first location for storing the data signal and a second location for storing the initialization status indicator. The sender performs initialization on the RAM at the beginning of a data transfer cycle which includes a plurality of data transfer from the sender to a receiver. The sender updates the initialization status indicator as the initialization progresses. The receiver reads the initialization status of the RAM from the second location and subsequently reads the data signal from the first location in association with the initialization status of the RAM.
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Banerjee Madhu B
DeRain David R
Dombrowski John R
Hesse Michael D
Joyce Mary
Bragdon Reginald G.
DaimlerChrysler Corporation
Smith Ralph E.
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